Thin film field effect transistor with amorphous oxide active layer and display using the same

• US 8,319,214 B2
• Filed: 11/12/2008
• Issued: 11/27/2012
• Est. Priority Date: 11/15/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Fujifilm Corporation (Fujifilm Holdings Corporation)
• Inventors: Imai, Shinji
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US12/292,070
• Publication Number:
  US 20090127551A1
• Time in Patent Office: 1,476 Days
• Field of Search: 257/43, 257/59, 257/49
• US Class Current: 257/43
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A TFT is provided which includes on a substrate, at least a gate electrode, a gate insulating layer, an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode, wherein a mean square interface roughness between the gate insulating layer and the active layer is less than 2 nm, a carrier concentration of the active layer is 1×10¹⁵ cm⁻³ or more, and a film thickness of the active layer is 0.5 nm or more and less than 20 nm. A TFT is provided which has high field effect mobility and a high ON-OFF ratio, and is improved in environmental temperature dependency. Also, a display using the TFT is provided.

Claims

1. A thin film field effect transistor comprising:

on an insulating substrate, at least a gate electrode, a gate insulating layer, an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode,

wherein a mean square interface roughness between the gate insulating layer and the active layer is less than 2 nm, a carrier concentration of the active layer is 1×

10¹⁵ cm<sup>−

3</sup> or more, and a film thickness of the active layer is 0.5 nm or more and less than 10 nm; and

a low carrier concentration layer that is in contact with the active layer on the opposite side of the active layer from the gate insulating layer and from the substrate, that has a carrier concentration of 10¹⁶ cm<sup>−

3</sup> or less, and that contains an amorphous oxide semiconductor.

2. The thin film field effect transistor according to claim 1, wherein the mean square interface roughness between the gate insulating layer and the active layer is less than 1 nm.

3. The thin film field effect transistor according to claim 1, wherein the mean square interface roughness between the gate insulating layer and the active layer is less than 0.5 nm, and the film thickness of the active layer is 0.5 nm or more and less than 5 nm.

4. The thin film field effect transistor according to claim 1, wherein the amorphous oxide semiconductor of the active layer contains at least one selected from the group consisting of In, Ga, Zn and Sn.

5. The thin film field effect transistor according to claim 1, wherein the amorphous oxide semiconductor of the low carrier concentration layer contains at least one selected from the group consisting of In, Ga, Zn and Sn.

6. The thin film field effect transistor according to claim 5, wherein the amorphous oxide semiconductor of the low carrier concentration layer contains at least one of In or Ga.

7. The thin film field effect transistor according to claim 1, wherein the gate insulating layer contains an amorphous oxide containing at least one element selected from the group consisting of Si, Hf, Y and Ge.

8. The thin film field effect transistor according to claim 1, wherein the insulating substrate is a flexible resin substrate.

9. The thin film field effect transistor according to claim 1, wherein the amorphous oxide semiconductor of the active layer contains at least one selected from the group consisting of In, Ga, Zn and Sn, and the amorphous oxide semiconductor of the low carrier concentration layer contains at least one selected from the group consisting of In, Ga, Zn and Sn.

10. The thin film field effect transistor according to claim 9, wherein the amorphous oxide semiconductor of the active layer and the amorphous oxide semiconductor of the low carrier concentration layer have compositions that are different from each other.

11. The thin film field effect transistor according to claim 1, wherein the gate insulating layer comprises an insulator selected from SiO₂, SiN_x, SiON, Ta₂O₅, or a mixed crystal compound containing at least two selected from SiO₂, SiN_x, SiON or Ta₂O₅.

12. The thin film field effect transistor according to claim 11, wherein a thickness of the gate insulating layer is from 10 nm to 10 μ

m.

13. The thin film field effect transistor according to claim 1, wherein the gate insulating layer comprises SiO₂.

14. The thin film field effect transistor according to claim 13, wherein a thickness of the gate insulating layer is from 10 nm to 10 μ

m.

15. A display using the thin film field effect transistor according to claim 1.