Device including nonvolatile memory element

• US 8,319,267 B2
• Filed: 11/10/2010
• Issued: 11/27/2012
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Ieda, Yoshinori, Koyama, Jun
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Parker, John M
• Application Number:
  US12/943,532
• Publication Number:
  US 20110114941A1
• Time in Patent Office: 748 Days
• Field of Search: 257/315, 257/324, 257/E21.422
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A device including a novel nonvolatile memory element is provided. A device including a nonvolatile memory element in which an oxide semiconductor is used as a semiconductor material for a channel formation region. The nonvolatile memory element includes a control gate, a charge accumulation layer which overlaps with the control gate with a first insulating film provided therebetween, and an oxide semiconductor layer formed using an oxide semiconductor material, which overlaps with the charge accumulation layer with a second insulating film provided therebetween.

Claims

1. A semiconductor device comprising:

a nonvolatile memory element and a transistor,

wherein the nonvolatile memory element comprises;

a control gate;

a charge accumulation layer overlapping with the control gate; and

a first oxide semiconductor layer including a channel formation region and overlapping with the charge accumulation layer,

wherein the transistor comprises;

a gate electrode; and

a second oxide semiconductor layer including a channel formation region and overlapping with the gate electrode with an insulating film interposed between the second oxide semiconductor layer and the gate electrode,

wherein the nonvolatile memory element and the transistor are electrically connected to each other.

2. A semiconductor device according to claim 1, the nonvolatile memory element further comprising:

a source electrode and a drain electrode which are electrically connected to the first oxide semiconductor layer,

wherein at least one of the source electrode and the drain electrode has a portion overlapping with the charge accumulation layer with an insulating film therebetween.

3. A semiconductor device according to claim 1,

wherein memory cells each including the nonvolatile memory element and the transistor are arranged in matrix.

4. A semiconductor device according to claim 1,

wherein a hydrogen concentration of the first and the second oxide semiconductor layers is less than or equal to 5×

10¹⁹/cm³.

5. A semiconductor device comprising:

a nonvolatile memory element and a transistor,

wherein the nonvolatile memory element comprises;

a control gate;

a charge accumulation layer overlapping with the control gate with a first insulating film therebetween; and

a first oxide semiconductor layer including a channel formation region and overlapping with the charge accumulation layer with a second insulating film therebetween,

wherein the transistor comprises;

a gate electrode; and

a second oxide semiconductor layer including a channel formation region and overlapping with the gate electrode with a third insulating film interposed between the second oxide semiconductor layer and the gate electrode,

wherein the nonvolatile memory element and the transistor are electrically connected to each other.

6. A semiconductor device according to claim 5, the nonvolatile memory element further comprising:

a source electrode and a drain electrode which are electrically connected to the oxide semiconductor layer,

wherein at least one of the source electrode and the drain electrode has a portion overlapping with the charge accumulation layer with the second insulating film therebetween.

7. A semiconductor device according to claim 5,

wherein memory cells each including the nonvolatile memory element and the transistor are arranged in matrix.

8. A semiconductor device according to claim 5,

wherein a hydrogen concentration of the first and the second oxide semiconductor layers is less than or equal to 5×

10¹⁹/cm³.

9. A semiconductor device comprising:

a nonvolatile memory element, the nonvolatile memory element comprising;

a control gate;

a charge accumulation layer overlapping with the control gate with a first insulating film therebetween; and

an oxide semiconductor layer including a channel formation region and overlapping with the charge accumulation layer with a second insulating film therebetween,

a source electrode and a drain electrode which are electrically connected to the oxide semiconductor layer,

wherein a width of the oxide semiconductor layer is larger than a width of the charge accumulation layer in a channel length direction,

wherein one of the source electrode and the drain electrode has a portion overlapping with the charge accumulation layer and in contact with the second insulating film, and

wherein the portion does not overlap with an end portion of the charge accumulation layer.

10. A semiconductor device according to claim 9,

wherein memory cells each including the nonvolatile memory element are arranged in matrix.

11. A semiconductor device according to claim 9 further comprising:

a transistor, the transistor comprising;

a gate electrode; and

a second oxide semiconductor layer including a channel formation region and overlapping with the gate electrode with a third insulating film between the second oxide semiconductor layer and the gate electrode.

12. A semiconductor device according to claim 11,

wherein the nonvolatile memory element and the transistor are electrically connected to each other.

13. A semiconductor device according to claim 11 further comprising:

memory cells each including the nonvolatile memory element and the transistor, which are arranged in matrix.

14. A semiconductor device according to claim 9,

wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹/cm³.