Semiconductor device and method for manufacturing the same
First Claim
1. A semiconductor device comprising:
- a semiconductor substrate which includes an active area surrounded by an element isolation insulation film; and
a non-volatile memory cell provided on the active area and including;
a tunnel insulation film provided on the active area;
a floating gate electrode provided on the tunnel insulation film;
a control gate electrode provided on the floating gate electrode; and
an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode,wherein, in a section of the non-volatile memory cell in a channel width direction,a dimension of a top face of the active area in the channel width direction is less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.
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Abstract
A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.
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Citations
8 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate which includes an active area surrounded by an element isolation insulation film; and a non-volatile memory cell provided on the active area and including;
a tunnel insulation film provided on the active area;
a floating gate electrode provided on the tunnel insulation film;
a control gate electrode provided on the floating gate electrode; and
an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode,wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification
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- Resources
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsMorikado, Mutsuo, Naruke, Kiyomi, Tsunoda, Hiroaki, Maruyama, Tohru, Arai, Fumitaka
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Primary Examiner(s)Toledo, Fernando L
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Assistant Examiner(s)Shamsuzzaman, Mohammed
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Application NumberUS12/642,073Publication NumberTime in Patent Office1,075 DaysField of Search257314-321US Class Current257/316CPC Class CodesH01L 29/40114 the electrodes comprising a...H01L 29/42336 with one gate at least part...H01L 29/66825 with a floating gate H01L29...H01L 29/7881 Programmable transistors wi...
