Power device structures and methods using empty space zones

• US 8,319,278 B1
• Filed: 03/10/2010
• Issued: 11/27/2012
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N., Blanchard, Richard A.
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): SNOW, COLLEEN ERIN
• Application Number:
  US12/720,856
• Time in Patent Office: 993 Days
• Field of Search: 257/340, 257/341, 257/E29.255, 257/330
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

Power semiconductor devices in which insulated empty space zones are used for field-shaping regions, in place of dielectric bodies previously used. Optionally permanent charge is added at the interface between the insulated empty space zone and an adjacent semiconductor drift region.

Claims

1. A semiconductor device, comprising:

at least one current-controlling structure, including a predominantly vertical channel region, and a gate which lies predominantly inside a first trench;

a drift region, into which majority carriers injected from said current-controlling structure flow when said current-controlling structure is in the ON state;

one or more insulated empty space zone-filled regions located within said first trench, in proximity to respective portions of said drift region; and

a drain, into which majority carriers flow from said drift region when said current-controlling structure is in the ON state;

wherein permanent electrostatic charge is located in proximity to sidewalls of said trench, to thereby apply a permanent electric field to said drift region near said trench.

2. The device of claim 1, wherein said gate lies entirely inside said trench.

3. The device of claim 1, wherein permanent electrostatic charge is located in proximity to at least one sidewall of said trench, to thereby cause inversion of a layer of said drift region near said sidewall of said trench, and thereby provide an induced drain extension region within said drift region.

4. The device of claim 1, further comprising a second trench which contains a field plate, but does not contain any gate electrode.

5. The device of claim 1, wherein said drift region and said drain region have different conductivity types.

6. The device of claim 1, wherein said drift region is doped p-type, and said majority carriers are electrons.

7. The device of claim 1, wherein said current-controlling structure comprises a first-conductivity-type source and a second-conductivity type body, and wherein said gate is positioned to controllably invert part of said body to form said channel therein.

8. The device of claim 1, wherein said drift region and said drain are formed in silicon.

9. A semiconductor device, comprising:

a first-conductivity-type semiconductor source;

a second-conductivity-type semiconductor body region, which separates said source from a semiconductor drift region;

a gate, located in a trench in said body region, which is capacitively coupled to a nearby portion of said body region to control formation of a channel therein; and

an insulated empty space zone region, also located in said trench in proximity to at least part of said drift region;

whereby capacitive coupling to said drift region is reduced by the lower parasitic capacitance of said empty space zone region;

and further comprising permanent electrostatic charges located in proximity to sidewalls of said trench.

10. The device of claim 9, wherein said gate lies entirely inside said trench.

11. The device of claim 9, further comprising a second trench which contains a field plate, but does not contain any gate electrode.

12. The device of claim 9, wherein said drift region and said body region are both doped p-type.

13. A semiconductor device, comprising:

a first-conductivity-type semiconductor source;

a second-conductivity-type semiconductor body region, which vertically separates said source from a semiconductor drift region;

a gate, located in a first part of a trench, which is capacitively coupled to a nearby portion of said body region to control formation of a channel therein;

an insulated empty space zone region, located in a second part of said trench, beneath said gate, in proximity to at least part of said drift region;

wherein said second part of said trench is narrower than said first part of said trench;

permanent electrostatic charge in proximity to an interface between said second part of said trench and said drift region; and

a first-conductivity-type drain region below said drift region;

whereby capacitive coupling to said drift region is reduced by the lower parasitic capacitance of said empty space zone region.

14. The device of claim 13, wherein said permanent electrostatic charge is present in proximity to vertical sidewalls of said second part of said trench, and not in proximity to vertical sidewalls of said first part of said trench.

15. The device of claim 13, wherein said gate lies entirely inside said first part of said trench.

16. The device of claim 13, further comprising an additional trench which contains a field plate, but does not contain any gate electrode.

17. The device of claim 13, wherein said drift region and said drain region have different conductivity types.

18. The device of claim 13, wherein majority carrier flow passes through said drift region to said drain region in a predominantly vertical direction.