Trench MOS barrier schottky rectifier with a planar surface using CMP techniques

• US 8,319,290 B2
• Filed: 06/18/2010
• Issued: 11/27/2012
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E.
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): KIM, SU C
• Application Number:
  US12/819,109
• Publication Number:
  US 20110309470A1
• Time in Patent Office: 893 Days
• Field of Search: 257/262, 257/272, 257/368, 257/369, 257/371, 257/374, 257/377, 257/383, 257/384, 257/396, 257/397, 257/647, 257/E29.02, 257/E29.271, 257/E21.552, 257/E21.553, 257/E21.555, 438/135, 438/142, 438/151, 438/197, 438/199, 438/201, 438/207, 438/216, 438/225, 438/226, 438/228, 438/230, 438/297, 438/362, 438/363, 438/439, 438/442
• US Class Current: 257/374
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Claims

1. A semiconductor device, comprising:

an epitaxial layer;

a silicide layer disposed on at least a portion of the epitaxial layer;

a field oxide extending into the epitaxial layer;

a substantially planar surface including a substantially planar region of the field oxide and a substantially planar region of the epitaxial layer, the substantially planar surface being in contact with a substantially planar bottom surface of the silicide layer;

a trench disposed in the epitaxial layer, the trench having a trench sidewall and a bottom;

a shield dielectric lining the trench sidewall and the bottom of the trench, the shield dielectric being disposed on at least a portion of the field oxide; and

a polysilicon disposed in the trench.

2. The semiconductor device of claim 1, wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).

3. The semiconductor device of claim 1, wherein the substantially planar surface is a contiguous surface.

4. The semiconductor device of claim 1, wherein silicide layer and the epitaxial layer form at least a portion of a Schottky rectifier.

5. The semiconductor device of claim 1, further comprising:

a mesa defining at least a portion of the trench sidewall of the trench, the substantially planar surface including a substantially planar region of the polysilicon, a substantially planar region of the shield dielectric and a substantially planar region of the mesa.

6. The semiconductor device of claim 1, wherein the substantially planar bottom surface of the silicide layer is in contact with at least a portion of the shield dielectric and at least a portion of the polysilicon.

7. The semiconductor device of claim 1, wherein the silicide layer is electrically coupled to the polysilicon disposed in the trench.

8. The semiconductor device of claim 1, wherein the substantially planar region is a substantially planar first region,

the semiconductor device further comprising:

a top metal having a first portion disposed above the field oxide and a second portion disposed on at least a portion of the silicide layer;

a dielectric layer;

a solderable top metal (STM) layer adjacent to the dielectric layer; and

a substantially planar second surface including a substantially planar region of the dielectric layer disposed on the first portion of the top metal, a substantially planar first region of the STM layer disposed on the first portion of the top metal, and a substantially planar second region of the STM layer disposed on the second portion of the top metal.

9. A semiconductor device, comprising:

an epitaxial layer;

a silicide layer disposed on at least a portion of the epitaxial layer;

a field oxide extending into the epitaxial layer;

a trench disposed in the epitaxial layer and below the silicide layer;

a top metal having a first portion disposed above the field oxide and a second portion disposed on at least a portion of the silicide layer;

a dielectric layer;

a solderable top metal (STM) layer adjacent to the dielectric layer; and

a substantially planar surface including a substantially planar region of the dielectric layer disposed on the first portion of the top metal, a substantially planar first region of the STM layer disposed on the first portion of the top metal, and a substantially planar second region of the STM layer disposed on the second portion of the top metal.

10. The semiconductor device of claim 9, wherein the substantially planar surface is formed using chemical mechanical planarization (CMP).

11. The semiconductor device of claim 9, wherein the substantially planar surface is a substantially planar first surface,

the semiconductor device further comprising:

a substantially planar second surface including a substantially planar region of the field oxide and a substantially planar region of the epitaxial layer, the substantially planar second surface being formed using chemical mechanical planarization (CMP).

12. The semiconductor device of claim 9, wherein the dielectric layer includes polyimide.

13. The semiconductor device of claim 9, wherein the silicide layer and the epitaxial layer form at least a portion of a Schottky rectifier.

14. The semiconductor device of claim 9, wherein the substantially planar surface is a substantially planar first surface,

the semiconductor device further comprising:

a polysilicon disposed in the trench;

a mesa defining at least a portion of a trench sidewall of the trench; and

a substantially planar second surface including a substantially planar region of the polysilicon, a substantially planar region of a shield dielectric disposed in the trench, and a substantially planar region of the mesa.

15. The semiconductor device of claim 9, wherein the trench has a trench sidewall and a bottom,

the semiconductor device further comprising:

a shield dielectric lining the trench sidewall and the bottom of the trench, the shield dielectric being disposed between the field oxide and the first portion of the top metal.

16. The semiconductor device of claim 9, wherein the trench has a trench sidewall and a bottom,

the semiconductor device further comprising:

a shield dielectric lining the trench sidewall and the bottom of the trench, the shield dielectric being disposed above at least a portion of the field oxide.

17. The semiconductor device of claim 9, further comprising:

a polysilicon disposed within the trench and coupled to the silicide layer, the STM layer being electrically coupled to the polysilicon via the top metal and the silicide layer.

18. The semiconductor device of claim 9, wherein the substantially planar surface is a substantially planar first surface,

the semiconductor device further comprising:

a substantially planar second surface including a substantially planar region of the field oxide and a substantially planar region of the epitaxial layer; and

a substantially planar third surface including a substantially planar region of polysilicon, and a substantially planar region of a shield dielectric disposed in the trench.

19. The semiconductor device of claim 9, wherein the STM layer includes at least one of Titanium, Nickel, Silver, Copper, or Tantalum.