Depletion MOS transistor and enhancement MOS transistor

• US 8,319,316 B2
• Filed: 05/27/2010
• Issued: 11/27/2012
• Est. Priority Date: 05/29/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kutsukake, Hiroyuki, Gomikawa, Kenji, Kato, Yoshiko, Noguchi, Mitsuhiro, Endo, Masato
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Nicely, Joseph C
• Application Number:
  US12/788,784
• Publication Number:
  US 20100301426A1
• Time in Patent Office: 915 Days
• Field of Search: 257/391, 257/402, 257/403, 257/607, 257/611, 257/E29.269, 257/E21.619
• US Class Current: 257/611
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a memory cell transistor with a charge layer formed on a semiconductor layer with a gate insulating film interposed therebetween; and

a peripheral circuit including at least a first transistor,

wherein the first transistor includes;

a first gate electrode disposed on a surface of the semiconductor layer with a first gate insulating film interposed therebetween;

a first channel region of a first conductivity type formed in the surface of the semiconductor layer close to a region located immediately below the first gate electrode, the first channel region having a first impurity concentration;

a first source region of the first conductivity type and a first drain region of the first conductivity type each formed in the surface of the semiconductor layer and each having a second impurity concentration higher than the first impurity concentration;

a first overlapping region of the first conductivity type formed in the surface of the semiconductor layer immediately below the first gate electrode where the first channel region overlaps the first source region and the first drain region, the first overlapping region having a third impurity concentration higher than the second impurity concentration;

a first contact region of the first conductivity type formed in at least a part of a surface of each of the first source region and the first drain region and having a fourth impurity concentration higher than the second impurity concentration; and

a first impurity diffusion region of the first conductivity type formed in a partial region of at least one of the first source region and the first drain region and having a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration, and

the first impurity diffusion region is formed in contact with the first contact region and away from the first overlapping region and positioned at least in a region between the first contact region and the first overlapping region.

2. The device according to claim 1, wherein the peripheral circuit further includes a second transistor, and

the second transistor includes:

a second gate electrode disposed on the surface of the semiconductor layer with a second gate insulating film interposed therebetween;

a second channel region of the first conductivity type formed in a portion of the surface of the semiconductor layer which includes the region located immediately below the second gate electrode, the second channel region having a sixth impurity concentration; and

a second source region of the first conductivity type and a second drain region of the first conductivity type each formed in the surface of the semiconductor layer and each having a seventh impurity concentration higher than the sixth impurity concentration.

3. The device according to claim 2, wherein the first impurity concentration is equal to the sixth impurity concentration, and

the third impurity concentration is equal to the seventh impurity concentration.

4. The device according to claim 1, wherein an impurity implanted into the first channel region is different from that into the first source region and the first drain region, and

is of the same as that into the first impurity diffusion region.

5. The device according to claim 1, wherein the first impurity diffusion region is formed in both of the first source region and the first drain region.

6. The device according to claim 1, wherein the first impurity diffusion region covers a side surface and a bottom surface of the first contact region.

7. The device according to claim 1, wherein the peripheral circuit further includes a second transistor,

the second transistor includes:

a second gate electrode disposed on the surface of the semiconductor layer with a second gate insulating film interposed therebetween;

a second source region of the first conductivity type and a second drain region of the first conductivity type each formed in the surface of the semiconductor layer and each having a sixth impurity concentration;

a second contact region of the first conductivity type formed in at least a part of a surface of each of the second source region and the second drain region and having a seventh impurity concentration higher than the sixth impurity concentration; and

a second impurity diffusion region of the first conductivity type formed in a partial region of each of the second source region and the second drain region and having an eighth impurity concentration higher than the sixth impurity concentration and lower than the seventh impurity concentration, and

the second impurity diffusion region is formed in contact with the second contact region and positioned at least in a region between the second contact region and the second gate electrode.

8. The device according to claim 7, wherein the second transistor further includes:

a second channel region of a second conductivity type opposite to the first conductivity type, the second channel region being formed in the surface of the semiconductor layer close to the region located immediately below the second gate electrode, the second channel region having a ninth impurity concentration; and

a first overlapping region of the first conductivity type formed in the surface of the semiconductor layer immediately below the second gate electrode where the second channel region overlaps the second source region and the second drain region, the first overlapping region having a higher resistivity than the second source region and the second drain region.

9. The device according to claim 8, wherein the second impurity diffusion region contacts the overlapping region.

10. The device according to claim 7, wherein the second impurity diffusion region covers a side surface and a bottom surface of the second contact region.

11. A depletion MOS transistor comprising:

a gate electrode disposed on a surface of a semiconductor layer with a gate insulating film interposed therebetween;

a channel region of a first conductivity type formed in the surface of the semiconductor layer close to a region located immediately below the gate electrode, the channel region having a first impurity concentration;

a source region of the first conductivity type and a drain region of the first conductivity type each formed in the surface of the semiconductor layer and each having a second impurity concentration higher than the first impurity concentration;

an overlapping region of the first conductivity type formed in the surface of the semiconductor layer immediately below the gate electrode where the channel region overlaps the source region and the drain region, the overlapping region having a third impurity concentration higher than the second impurity concentration;

a contact region of the first conductivity type formed in at least a part of a surface of each of the source region and the drain region and having a fourth impurity concentration higher than the second impurity concentration; and

an impurity diffusion region of the first conductivity type formed in a partial region of at least one of the source region and the drain region and having a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration,

wherein the impurity diffusion region is formed in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.

12. The transistor according to claim 11, wherein an impurity implanted into the channel region is different from that into the source region and the drain region, and

is of the same as that into the impurity diffusion region.

13. The transistor according to claim 11, wherein the impurity diffusion region is formed in both of the source region and the drain region.

14. The transistor according to claim 11, wherein the impurity diffusion region covers a side surface and a bottom surface of the contact region.