Reduction of etch microloading for through silicon vias

• US 8,319,336 B2
• Filed: 07/08/2010
• Issued: 11/27/2012
• Est. Priority Date: 07/08/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Hung-Pin, Yu, Chen-Hua
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US12/832,184
• Publication Number:
  US 20120007132A1
• Time in Patent Office: 873 Days
• Field of Search: 257/99, 257/718, 257/720
• US Class Current: 257/718
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48229 the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2933/0075 : relating to heat extraction or cooling elements
• CPC Class Codes: H01L 33/642 : characterized by the shape
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

The patterns (or layout), and pattern densities of TSVs described above provide layout of TSVs that could be etched with reduced etch microloading effect(s) and with good within-die uniformity. The patterns and pattern densities of TSVs for different groups of TSVs (or physically separated groups, or groups with different functions) should be fairly close amongst different groups. Different groups of TSVs (or TSVs with different functions, or physically separated TSV groups) should have relatively close shapes, sizes, and depths to allow the aspect ratio of all TSVs to be within a controlled (and optimal) range. The size(s) and depths of TSVs should be carefully selected to optimize the etching time and the metal gap-fill time.

Claims

1. A package of a light-emitting device (LED) chip, comprising

the LED chip;

and

a support structure, wherein the LED chip is disposed on the support structure, and wherein the support structure has a first group of through silicon vias (TSVs) for providing electrical connection for the LED chip and a second group of TSVs for providing a function of heat dissipation for the LED chip, wherein the first group of TSVs are arranged in a first pattern with a first pattern density and the second group of TSVs are arranged in a second pattern with a second pattern density, and wherein the first and the second groups of TSVs all have a same depth and the first pattern of the first group of TSVs and the second pattern of the second group of TSVs are the same.

2. The package of claim 1, wherein the first group of TSVs and the second group of TSVs have significantly same shapes, significantly same sizes, and significantly same aspect ratios.

3. The package of claim 1, wherein first pattern density of the first group of TSVs and the second pattern density of the second group of TSVs are significantly the same.

4. The package of claim 1, wherein the first group of TSVs and the second group of TSVs all have a cross-sectional shape selected from a group consisting of circle, oval, square, rectangle, triangle, hexagonal, and octagonal.

5. The package of claim 1, wherein each of the first pattern density and the second pattern density is between about 25% to about 60%.

6. The package of claim 1, wherein absolute value of a difference between the first pattern density and the second pattern density has an absolute value between about 0.1% to about 5%.

7. The package of claim 6, wherein the first pattern density is higher than the second pattern density to reduce the edge effect of the first group of TSVs.

8. The package of claim 1, wherein the second group of TSVs also provide electrical connection for the LED.

9. The package of claim 1, wherein the second group of TSVs are disposed below the LED.

10. The package of claim 1, wherein aspect ratio of each of the first group of TSVs and second group of TSVs is between about 3 to about 10.

11. The package of claim 1, wherein a width of each of the first group of TSVs and the second group of TSVs is between about 15 μ

m to about 40 and wherein the depth of each of the first group of TSVs and the second group of TSVs is between about 30 μ

m to about 400 μ

m.

12. A semiconductor device comprising:

the semiconductor device; and

a support structure, wherein the semiconductor device is disposed on the support structure, and wherein the support structure has a first group of through silicon vias (TSVs) for providing electrical connection for the semiconductor device and a second group of TSVs for providing a function of heat dissipation for the semiconductor device, wherein the first group of TSVs are arranged in a first pattern with a first pattern density and the second group of TSVs are arranged in a second pattern with a second pattern density, and wherein the first and the second groups of TSVs all have a same depth and an absolute value of a difference between the first pattern density and the second pattern density has an absolute value between about 0.1% to about 5%.

13. The semiconductor device of claim 12, wherein the second group of TSVs is positioned between a first portion of the first group of TSVs and a second portion of the first group of TSVs.

14. The semiconductor device of claim 12, wherein a distance between TSVs within the first group of TSVs and within the second group of TSVs is equal to a diameter of the TSVs.

15. The semiconductor device of claim 12, wherein the first group of TSVs includes at least two first columns of TSVs, the second group of TSVs includes at least one second column of TSVs, and the at least two first columns of TSVs are arranged in alternating fashion with the at least one second column of TSVs.

16. The semiconductor device of claim 15, wherein the at least one second column of TSVs is offset from the at least two first columns of TSVs in a direction perpendicular to a line connecting the at least two first columns of TSVs.

17. The semiconductor device of claim 12, wherein a distance between the first group of TSVs and the second group of TSVs is greater than a distance between TSVs within the second group of TSVs.

18. The semiconductor device of claim 12, wherein a number of TSVs in the second group of TSVs is greater than a number of TSVs in the first group of TSVs.

19. The semiconductor device of claim 12, wherein the first group of TSVs are connected to an electrical interface, and the second group of TSVs are connected to a thermal interface separate from the electrical interface.

20. A semiconductor device comprising:

the semiconductor device; and

a support structure, wherein the semiconductor device is disposed on the support structure, and wherein the support structure has a first group of through silicon vias (TSVs) connected to an electrical interface for providing electrical connection for the semiconductor device and a second group of TSVs connected to a thermal interface for providing a function of heat dissipation for the semiconductor device, wherein the thermal interface is separate from the electrical interface, the first group of TSVs are arranged in a first pattern with a first pattern density and the second group of TSVs are arranged in a second pattern with a second pattern density, and the first and the second groups of TSVs all have a same depth.