Semiconductor chip with post-passivation scheme formed over passivation layer

• US 8,319,354 B2
• Filed: 07/12/2011
• Issued: 11/27/2012
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lo, Hsin-Jung, Chou, Chien-Kang, Chou, Chiu-Ming, Lin, Ching-San
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/181,255
• Publication Number:
  US 20110266669A1
• Time in Patent Office: 504 Days
• Field of Search: 257/E23.02, 257/E23.021, 257/E23.161, 257/506, 257/723, 257/737, 257/758, 257/780, 257/784, 257/786, 257/781, 438/106, 438/108, 438/132, 438/612, 438/614, 438/617
• US Class Current: 257/781
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05173 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05176 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05673 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05676 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13169 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13173 : Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/13176 : Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/4554 : Coating
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48477 : being a pre-ball (i.e. a ball formed by capillary bonding)
• CPC Class Codes: H01L 2224/4943 : the connecting portions being staggered
• CPC Class Codes: H01L 2224/85051 : Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Claims

1. A chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

an insulating layer over said first and second metal layers and said dielectric layer, wherein said insulating layer comprises a nitride layer;

a first metal interconnect having a first contact point at a bottom of a first opening in said insulating layer, wherein said first opening is over said first contact point;

a second metal interconnect having a second contact point at a bottom of a second opening in said insulating layer, wherein said second opening is over said second contact point;

a third metal interconnect having a third contact point at a bottom of a third opening in said insulating layer, wherein said third opening is over said third contact point, wherein said first, second and third metal interconnects comprise electroplated copper, wherein said first, second and third contact points are aligned in a first line, wherein said second contact point is between said first and third contact points;

a patterned metal layer on said first, second and third contact points and over said insulating layer, wherein said patterned metal layer comprises a first adhesion layer and a third metal layer over said first adhesion layer, wherein said third metal layer has a sidewall not covered by said first adhesion layer, wherein said patterned metal layer comprises a first metal trace over said insulating layer, wherein said first metal trace is connected to said first contact point through said first opening, a first contact pad connected to said first contact point through said first metal trace, wherein said first contact pad is not vertically over said first contact point, a second metal trace over said insulating layer, wherein said second metal trace is connected to said second contact point through said second opening, a second contact pad connected to said second contact point through said second metal trace, wherein said second contact pad is not vertically over said second contact point, a third metal trace over said insulating layer, wherein said third metal trace is connected to said third contact point through said third opening, and a third contact pad connected to said third contact point through said third metal trace, wherein said third contact pad is not vertically over said third contact point, wherein said second metal trace extends between said first and third contact pads;

a first metal bump on said first contact pad and not vertically over said first contact point, wherein said first metal bump comprises a second adhesion layer and a gold layer with a height between 1 and 50 micrometers over said second adhesion layer;

a second metal bump on said second contact pad and not vertically over said second contact point; and

a third metal bump on said third contact pad and not vertically over said third contact point, wherein said first and third metal bumps are aligned in a second line substantially parallel with said first line.

2. The chip of claim 1, wherein said insulating layer comprises an oxide.

3. The chip of claim 1, wherein said insulating layer comprises a nitride.

4. The chip of claim 1, wherein said insulating layer comprises an oxide layer having a thickness between 0.2 and 1 micrometer.

5. The chip of claim 1, wherein said second adhesion layer comprises titanium.

6. The chip of claim 1, wherein said gold layer has more than 95 percent by weight of gold.

7. The chip of claim 1, wherein said first adhesion layer comprises titanium.

8. The chip of claim 1, wherein said third metal layer comprises copper.

9. The chip of claim 1, wherein no polymer layer is between said patterned metal layer and said insulating layer.

10. The chip of claim 1 further comprising a capping layer on said patterned metal layer.

11. A chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

an insulating layer over said first and second metal layers and said dielectric layer, wherein said insulating layer comprises a nitride layer;

a first metal interconnect having a first contact point at a bottom of a first opening in said insulating layer, wherein said first opening is over said first contact point;

a second metal interconnect having a second contact point at a bottom of a second opening in said insulating layer, wherein said second opening is over said second contact point;

a third metal interconnect having a third contact point at a bottom of a third opening in said insulating layer, wherein said third opening is over said third contact point, wherein said first, second and third metal interconnects comprise electroplated copper, wherein said first, second and third contact points are aligned in a first line, wherein said second contact point is between said first and third contact points;

a patterned metal layer on said first, second and third contact points and over said insulating layer, wherein said patterned metal layer comprises a first adhesion layer and a third metal layer over said first adhesion layer, wherein said third metal layer has a sidewall not covered by said first adhesion layer;

a first metal bump on said patterned metal layer, wherein said patterned metal layer connects said first metal bump to said first contact point through said first opening, wherein said first metal bump comprises a second adhesion layer and a gold layer with a height between 1 and 50 micrometers over said second adhesion layer;

a second metal bump on said patterned metal layer, wherein said patterned metal layer connects said second metal bump to said second contact point through said second opening; and

a third metal bump on said patterned metal layer, wherein said patterned metal layer connects said third metal bump to said third contact point through said third opening, wherein said first, second and third metal bumps are aligned in a second line substantially parallel with said first line.

12. The chip of claim 11, wherein said insulating layer comprises an oxide.

13. The chip of claim 11, wherein said insulating layer comprises a nitride.

14. The chip of claim 11, wherein said insulating layer comprises an oxide layer having a thickness between 0.2 and 1 micrometer.

15. The chip of claim 11, wherein said second adhesion layer comprises titanium.

16. The chip of claim 11, wherein said gold layer has more than 95 percent by weight of gold.

17. The chip of claim 11, wherein said first adhesion layer comprises titanium.

18. The chip of claim 11, wherein said third metal layer comprises copper.

19. The chip of claim 11, wherein no polymer layer is between said patterned metal layer and said insulating layer.

20. The chip of claim 11 further comprising a capping layer on said patterned metal layer.

21. A chip comprising:

a silicon substrate;

a MOS device in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper;

a second dielectric layer over said first dielectric layer and between said first and second metal layers;

an insulating layer over said metallization structure and said first and second dielectric layers, wherein a first opening in said insulating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said insulating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said insulating layer comprises a nitride layer;

a patterned metal layer on said first and second contact points and over said insulating layer, wherein said patterned metal layer comprises a first metal interconnect connected to said first contact point through said first opening, a second metal interconnect connected to said second contact point through said second opening, and a third metal interconnect between said first and second metal interconnects, wherein said patterned metal layer comprises a first adhesion layer and a third metal layer over said first adhesion layer, wherein said third metal layer has a sidewall not covered by said first adhesion layer;

a first metal bump on said first metal interconnect and vertically over said first contact point;

a second metal bump on said second metal interconnect and vertically over said second contact point, wherein there is no metal bump between said first and second metal bumps, wherein said third metal interconnect has a portion between and spaced apart from said first metal interconnect vertically under said first metal bump and said second metal interconnect vertically under said second metal bump; and

a third metal bump aligned with said first and second metal bumps.

22. The chip of claim 21 further comprising a polymer layer over said patterned metal layer.

23. The chip of claim 21, wherein said first metal bump comprises a second adhesion layer on said first metal interconnect and a copper layer over said second adhesion layer.

24. The chip of claim 23, wherein said second adhesion layer comprises titanium.

25. The chip of claim 23, wherein said copper layer has a thickness between 0.5 and 10 micrometers.

26. The chip of claim 23, wherein said first metal bump further comprises a nickel layer on said copper layer.

27. The chip of claim 26, wherein said nickel layer has a thickness between 0.5 and 10 micrometers.

28. The chip of claim 26, wherein said first metal bump further comprises a tin-containing layer on said nickel layer.

29. The chip of claim 21, wherein said insulating layer comprises an oxide.

30. The chip of claim 21, wherein said insulating layer comprises a nitride.

31. The chip of claim 21, wherein said insulating layer comprises an oxide layer having a thickness between 0.2 and 1 micrometer.

32. The chip of claim 21, wherein said third metal layer comprises copper.

33. The chip of claim 21, wherein no polymer layer is between said patterned metal layer and said insulating layer.