Systems and methods for adjusting threshold voltage

• US 8,319,515 B2
• Filed: 08/25/2009
• Issued: 11/27/2012
• Est. Priority Date: 02/02/2004
• Status: Expired due to Term

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert Paul, Burr, James B.
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US12/547,416
• Publication Number:
  US 20090309626A1
• Time in Patent Office: 1,190 Days
• Field of Search: None
• US Class Current: 324/762.09
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

Claims

1. An apparatus comprising:

means for measuring a threshold voltage of a transistor of an integrated circuit;

means for determining a bias voltage which, responsive to application to a body well of said transistor, reduces a difference between said threshold voltage and a desired threshold voltage for said transistor; and

means for encoding said bias voltage into non-volatile storage on said integrated circuit.

2. The apparatus of claim 1 wherein said transistor is a p channel field effect transistor.

3. The apparatus of claim 1 wherein said transistor is an n channel field effect transistor.

4. The apparatus of claim 1 wherein said non-volatile storage comprises a fuse.

5. The apparatus of claim 1 wherein said non-volatile storage comprises electrically erasable programmable read only memory.

6. The apparatus of claim 1 wherein said means for encoding comprises means for storing a digital representation of said bias voltage.

7. The apparatus of claim 6 wherein said digital representation of said bias voltage is accessible by a bias voltage source.

8. The apparatus of claim 6 wherein said digital representation of said bias voltage is accessible by a microprocessor.

9. The apparatus of claim 1 wherein said means for encoding comprises means for storing an analog representation of said bias voltage.

10. The apparatus of claim 9 wherein said analog representation of said bias voltage is accessible by a bias voltage source.

11. The apparatus of claim 1 wherein said desired threshold voltage is a nominal process threshold voltage for said integrated circuit.

12. The apparatus of claim 1 wherein said desired threshold voltage is determined based on power consumption characteristics of said integrated circuit at a specific operating frequency.

13. An apparatus comprising:

circuitry configured to measure a threshold voltage of a transistor of an integrated circuit;

circuitry configured to determine a bias voltage which, responsive to application to a body well of said transistor, reduces a difference between said threshold voltage and a desired threshold voltage for said transistor; and

circuitry configured to encode said bias voltage into non-volatile storage on said integrated circuit.

14. The apparatus of claim 13 wherein said transistor is a p channel field effect transistor.

15. The apparatus of claim 13 wherein said transistor is an n channel field effect transistor.

16. The apparatus of claim 13 wherein said non-volatile storage comprises a fuse.

17. The apparatus of claim 13 wherein said non-volatile storage comprises electrically erasable programmable read only memory.

18. The apparatus of claim 13 wherein said circuitry configured to encode comprises circuitry for storing a digital representation of said bias voltage.

19. The apparatus of claim 18 wherein said digital representation of said bias voltage is accessible by a bias voltage source.

20. The apparatus of claim 18 wherein said digital representation of said bias voltage is accessible by a microprocessor.

21. The apparatus of claim 13 wherein said desired threshold voltage is a nominal process threshold voltage for said integrated circuit.

22. The apparatus of claim 13 wherein said desired threshold voltage is determined based on power consumption characteristics of said integrated circuit at a specific operating frequency.

23. The apparatus of claim 13 further comprising:

circuitry configured to generate said bias voltage; and

circuitry configured to apply said bias voltage to a body biasing well of said integrated circuit.

24. An apparatus comprising:

circuitry configured to measure a threshold voltage of a transistor of an integrated circuit;

circuitry configured to determine a bias voltage which, responsive to application to a body well of said transistor, reduces a difference between said unbiased threshold voltage and a desired threshold voltage for said transistor;

circuitry configured to encode said bias voltage into non-volatile storage on said integrated circuit; and

circuitry configured to apply said body bias voltage to said transistor to achieve said desired threshold voltage.