Semiconductor device having interconnected transistors and electronic device including semiconductor device
First Claim
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1. A semiconductor device comprising:
- a first transistor including a gate, a source and a drain;
a second transistor including a gate, a source and a drain;
a third transistor including a gate, a source and a drain;
a fourth transistor including a gate, a source and a drain;
a fifth transistor including a gate, a source and a drain;
a sixth transistor including a gate, a source and a drain; and
a seventh transistor including a gate, a source and a drain,wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal,wherein one of the source and the drain of the second transistor is electrically connected to a second input terminal,wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor,wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor,wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor,wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor,wherein one of the source and the drain of the third transistor is electrically connected to a first line,wherein one of the source and the drain of the fourth transistor is electrically connected to the first line,wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal,wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal,wherein the gate of the fifth transistor is electrically connected to a third input terminal,wherein the gate of the sixth transistor is electrically connected to the third input terminal,wherein the gate of the seventh transistor is electrically connected to the third input terminal,wherein one of the source and the drain of the fifth transistor is electrically connected to a second line,wherein one of the source and the drain of the sixth transistor is electrically connected to the second line,wherein one of the source and the drain of the seventh transistor is electrically connected to the second line,wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor,wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, andwherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal.
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Abstract
It is an object to suppress deterioration in characteristics of a transistor in a driver circuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off.
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Citations
26 Claims
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1. A semiconductor device comprising:
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a first transistor including a gate, a source and a drain; a second transistor including a gate, a source and a drain; a third transistor including a gate, a source and a drain; a fourth transistor including a gate, a source and a drain; a fifth transistor including a gate, a source and a drain; a sixth transistor including a gate, a source and a drain; and a seventh transistor including a gate, a source and a drain, wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal, wherein one of the source and the drain of the second transistor is electrically connected to a second input terminal, wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor, wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor, wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of the source and the drain of the third transistor is electrically connected to a first line, wherein one of the source and the drain of the fourth transistor is electrically connected to the first line, wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal, wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal, wherein the gate of the fifth transistor is electrically connected to a third input terminal, wherein the gate of the sixth transistor is electrically connected to the third input terminal, wherein the gate of the seventh transistor is electrically connected to the third input terminal, wherein one of the source and the drain of the fifth transistor is electrically connected to a second line, wherein one of the source and the drain of the sixth transistor is electrically connected to the second line, wherein one of the source and the drain of the seventh transistor is electrically connected to the second line, wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, and wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device comprising:
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a first transistor including a gate, a source and a drain; a second transistor including a gate, a source and a drain; a third transistor including a gate, a source and a drain; a fourth transistor including a gate, a source and a drain; a fifth transistor including a gate, a source and a drain; a sixth transistor including a gate, a source and a drain; and a seventh transistor including a gate, a source and a drain, wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal, wherein the of the source and the drain of the second transistor is electrically connected to a second input terminal, wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor, wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor, wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of the source and the drain of the third transistor is electrically connected to a first line, wherein one of the source and the drain of the fourth transistor is electrically connected to the first line, wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal, wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal, wherein the gate of the fifth transistor is electrically connected to a third input terminal, wherein the gate of the sixth transistor is electrically connected to the third input terminal, wherein the gate of the seventh transistor is electrically connected to the third input terminal, wherein one of the source and the drain of the fifth transistor is electrically connected to a second line, wherein one of the source and the drain of the sixth transistor is electrically connected to the second line, wherein one of the source and the drain of the seventh transistor is electrically connected to the second line, wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal, and wherein polarities of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are the same. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor device comprising:
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a shift register comprising; a first transistor including a gate, a source and a drain; a second transistor including a gate, a source and a drain; a third transistor including a gate, a source and a drain; a fourth transistor including a gate, a source and a drain; a fifth transistor including a gate, a source and a drain; a sixth transistor including a gate, a source and a drain; and a seventh transistor including a gate, a source and a drain, wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal, wherein one of the source and the drain of the second transistor is electrically connected to a second input terminal, wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor, wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor, wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of the source and the drain of the third transistor is electrically connected to a first line, wherein one of the source and the drain of the fourth transistor is electrically connected to the first line, wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal, wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal, wherein the gate of the fifth transistor is electrically connected to a third input terminal, wherein the gate of the sixth transistor is electrically connected to the third input terminal, wherein the gate of the seventh transistor is electrically connected to the third input terminal, wherein one of the source and the drain of the fifth transistor is electrically connected to a second line, wherein one of the source and the drain of the sixth transistor is electrically connected to the second line, wherein one of the source and the drain of the seventh transistor is electrically connected to the second line, wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, and wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal. - View Dependent Claims (12, 13, 14, 15)
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16. A semiconductor device comprising:
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a shift resister comprising; a first transistor including a gate, a source and a drain; a second transistor including a gate, a source and a drain; a third transistor including a gate, a source and a drain; a fourth transistor including a gate, a source and a drain; a fifth transistor including a gate, a source and a drain; a sixth transistor including a gate, a source and a drain; and a seventh transistor including a gate, a source and a drain, wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal, wherein one of the source and the drain of the second transistor is electrically connected to a second input terminal, wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor, wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor, wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of the source and the drain of the third transistor is electrically connected to a first line, wherein one of the source and the drain of the fourth transistor is electrically connected to the first line, wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal, wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal, wherein the gate of the fifth transistor is electrically connected to a third input terminal, wherein the gate of the sixth transistor is electrically connected to the third input terminal, wherein the gate of the seventh transistor is electrically connected to the third input terminal, wherein one of the source and the drain of the fifth transistor is electrically connected to a second line, wherein one of the source and the drain of the sixth transistor is electrically connected to the second line, wherein one of the source and the drain of the seventh transistor is electrically connected to the second line, wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal, and wherein polarities of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are the same. - View Dependent Claims (17, 18, 19, 20)
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21. A semiconductor device comprising:
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a shift register comprising a flip-flop circuit comprising; a first transistor including a gate, a source and a drain; a second transistor including a gate, a source and a drain; a third transistor including a gate, a source and a drain; a fourth transistor including a gate, a source and a drain; a fifth transistor including a gate, a source and a drain; a sixth transistor including a gate, a source and a drain; and a seventh transistor including a gate, a source and a drain, wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal, wherein one of the source and the drain of the second transistor is electrically connected to a second input terminal, wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor, wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor, wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of the source and the drain of the third transistor is electrically connected to a first line, wherein one of the source and the drain of the fourth transistor is electrically connected to the first line, wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal, wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal, wherein the gate of the fifth transistor is electrically connected to a third input terminal, wherein the gate of the sixth transistor is electrically connected to the third input terminal, wherein the gate of the seventh transistor is electrically connected to the third input terminal, wherein one of the source and the drain of the fifth transistor is electrically connected to a second line, wherein one of the source and the drain of the sixth transistor is electrically connected to the second line, wherein one of the source and the drain of the seventh transistor is electrically connected to the second line, wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, and wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal. - View Dependent Claims (22, 23, 24, 25)
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26. A semiconductor device comprising:
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a shift register comprising a flip-flop circuit comprising; a first transistor including a gate, a source and a drain; a second transistor including a gate, a source and a drain; a third transistor including a gate, a source and a drain; a fourth transistor including a gate, a source and a drain; a fifth transistor including a gate, a source and a drain; a sixth transistor including a gate, a source and a drain; and a seventh transistor including a gate, a source and a drain, wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal, wherein one of the source and the drain of the second transistor is electrically connected to a second input terminal, wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor, wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor, wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, wherein one of the source and the drain of the third transistor is electrically connected to a first line, wherein one of the source and the drain of the fourth transistor is electrically connected to the first line, wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal, wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal, wherein the gate of the fifth transistor is electrically connected to a third input terminal, wherein the gate of the sixth transistor is electrically connected to the third input terminal, wherein the gate of the seventh transistor is electrically connected to the third input terminal, wherein one of the source and the drain of the fifth transistor is electrically connected to a second line, wherein one of the source and the drain of the sixth transistor is electrically connected to the second line, wherein one of the source and the drain of the seventh transistor is electrically connected to the second line, wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal, and wherein polarities of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are the same.
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsKimura, Hajime, Umezaki, Atsushi
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Primary Examiner(s)Wells, Kenneth B.
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Application NumberUS12/730,976Publication NumberTime in Patent Office979 DaysField of Search327/108, 326/87, 345/100US Class Current327/108CPC Class CodesG09G 2310/0286 Details of a shift register...G09G 2320/043 Preventing or counteracting...G09G 3/3614 Control of polarity reversa...G09G 3/3677 suitable for active matrice...G09G 3/3688 suitable for active matrice...G11C 19/28 using semiconductor element...H03K 19/00369 Modifications for compensat...
