In-plane switching mode liquid crystal display having at least one common line underneath a respective common electrode to overlap the common electrode

• US 8,319,903 B2
• Filed: 10/08/2008
• Issued: 11/27/2012
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Oh, Jae-Young, Lee, Joon-Youp, Jin, Hyun-Cheol, Lee, Min-Jic
• Primary Examiner(s): Robinson, Mark
• Assistant Examiner(s): LEE, PAUL CHANG
• Application Number:
  US12/247,779
• Publication Number:
  US 20090102994A1
• Time in Patent Office: 1,511 Days
• Field of Search: 349/38, 349/39, 349/42, 349/140, 349/141, 349/142, 349/149
• US Class Current: 349/39
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

An in-plane switching mode liquid crystal display according to an embodiment includes gate lines arranged in a first direction on an array substrate, data lines arranged in a second direction substantially perpendicular to the first direction, one or more storage electrodes provided on the array substrate, common electrodes extending across each pixel region, pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region, thin film transistors (TFTs) provided at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode, and at least one common line located under the respective common electrode in the pixel region, the common line being substantially parallel to the data lines.

Claims

1. An in-plane switching (IPS) mode liquid crystal display (LCD), comprising:

a gate electrode on an array substrate, and a gate line arranged in a first direction on the array substrate;

one or more storage electrodes arranged in a second direction substantially perpendicular to the first direction on the array substrate;

a first insulating layer on the array substrate with the gate electrode, the gate line and the storage electrodes formed thereon;

an active pattern over the gate electrode with the first insulating layer interposed therebetween;

a source electrode and a drain electrode on the active pattern, and a data line arranged in the second direction over the first insulating layer;

at least one common line arranged in the second direction over the first insulating layer;

a second insulating layer on the array substrate with the active pattern, the source and drain electrodes, the data line and the common line formed thereon;

a plurality of common electrodes on the second insulating layer, wherein the common line is underneath the respective common electrode to overlap the common electrode; and

a plurality of pixel electrodes arranged to be substantially parallel to the plurality of common electrodes on the second insulating layer, the plurality of common electrodes and the plurality of pixel electrodes being alternately arranged to generate an in-plane field in each pixel region.

2. The IPS mode LCD of claim 1, wherein the common line and the data line are made of the same conductive material and the common line is provided on the layer on which the data lines are formed.

3. The IPS mode LCD of claim 1, wherein the common line traverses the corresponding gate line with the first insulating layer interposed between the common line and the gate line to prevent the corresponding gate line from short-circuiting with the common line.

4. The IPS mode LCD of claim 1, wherein a length of the common line extending across an entire region of the IPS mode LCD is shorter than a length of at least one of the gate lines extending across the entire region of the IPS mode LCD.

5. The IPS mode LCD of claim 1, wherein the common electrodes and the pixel electrodes are bent or curved at one or more portions.

6. The IPS mode LCD of claim 1, wherein a first connection line is connected with the common electrodes, the first connection line being substantially parallel to the gate lines.

7. The IPS mode LCD of claim 6, wherein a second connection line is connected with the pixel electrodes, the second connection line being electrically connected with the drain electrode and the storage electrodes.

8. The IPS mode LCD of claim 7, wherein the second connection line is electrically connected with the drain electrode and the storage electrodes via a first contact hole and second contact holes, respectively.

9. The IPS mode LCD of claim 7, wherein at least one of the common electrodes, the pixel electrodes, the first connection line and the second connection line is made of a transparent conductive material.

10. The IPS mode LCD of claim 1, wherein the common electrodes includes outermost common electrodes provided at edges of each pixel region.

11. The IPS mode LCD of claim 10, wherein the outermost common electrodes overlap with storage electrodes to form storage capacitors with first and second insulating layers interposed between the outermost common electrodes and the storage electrodes.

12. The IPS mode LCD of claim 6, wherein the common line is electrically connected with the first connection line via a third contact hole provided at a second insulating layer to supply a common voltage to the first connection line and the common electrodes.

13. The IPS mode LCD of claim 1, wherein the at least one common line includes first and second common lines provided under the respective common electrodes in the corresponding pixel region, the first and second common lines being substantially parallel to the data lines.

14. The IPS mode LCD of claim 1, wherein the one or more storage electrodes constitute a single storage electrode provided at one edge portion of a pixel area to form a single storage capacitor.