High-efficiency, switched-capacitor power conversion using a resonant clocking circuit to produce gate drive signals for switching capacitors

• US 8,320,141 B2
• Filed: 08/05/2009
• Issued: 11/27/2012
• Est. Priority Date: 08/05/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Athas, William C., Ungar, P. Jeffrey
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): NASH, GARY A
• Application Number:
  US12/535,974
• Publication Number:
  US 20110031956A1
• Time in Patent Office: 1,210 Days
• Field of Search: 323/242, 323/288, 323/290, 363/21.02, 363/21.03, 363 59- 61
• US Class Current: 363/59
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

Some embodiments of the present invention provide a system that efficiently converts between a lower input voltage and a higher output voltage. This system includes an input which receives the input voltage, and an output which provides the output voltage. The system also includes a first capacitor with a higher potential terminal and a lower potential terminal, as well as a first set of switching devices which selectively couple the higher potential and lower potential terminals of the first capacitor between the input voltage, the output voltage and a base voltage. The system additionally includes a resonant clocking circuit which generates clock signals with substantially non-overlapping clock phases, including a first phase and a second phase. This resonant clocking circuit is configured to control the first set of switching devices so that during the first phase, the higher potential terminal of the first capacitor is coupled to the input voltage and the lower potential terminal of the first capacitor is coupled to the base voltage, and during the second phase, the higher potential terminal of the first capacitor is coupled to the output voltage and the lower potential terminal of the first capacitor is coupled to the input voltage.

Claims

1. A system for converting between an input voltage and an output voltage, comprising:

an input coupled to the input voltage;

an output coupled to the output voltage;

a first and a second capacitor, each with a higher potential terminal and a lower potential terminal;

a first set of switching devices which selectively couple the higher potential and lower potential terminals of the first capacitor between the input voltage, the output voltage and a base voltage;

a second set of switching devices; and

a resonant clocking circuit which generates clock signals with substantially non-overlapping clock phases, including a first phase and a second phase, for the first set of switching devices;

wherein the resonant clocking circuit is configured to control the first set of switching devices so that during the first phase the higher potential terminal of the first capacitor is coupled to the input voltage and the lower potential terminal of the first capacitor is coupled to the base voltage, and during the second phase the higher potential terminal of the first capacitor is coupled to the output voltage and the lower potential terminal of the first capacitor is coupled to the input voltage,

wherein the resonant clocking circuit is configured to control the second set of switching devices so that during the first phase the higher potential terminal of the second capacitor is coupled to the output voltage and the lower potential terminal of the second capacitor is coupled to the input voltage, and during the second phase the higher potential terminal of the second capacitor is coupled to the input voltage and the lower potential terminal of the second capacitor is coupled to the base voltage.

2. The system of claim 1, wherein the resonant clocking circuit is an LC oscillator circuit which includes at least one inductance and at least one capacitance.

3. The system of claim 2, wherein the at least one capacitance is a gate of a charge-controlled switching device which is used to implement a switching device in the first set of switching devices.

4. The system of claim 1, further comprising a battery that provides the input voltage, wherein a lower potential terminal of the battery is coupled to the base voltage and a higher potential terminal of the battery is coupled to the input, and wherein the battery includes one or more battery cells which are coupled in parallel between the input and the base voltage.

5. The system of claim 1, further comprising a capacitor coupled between the output and the input.

6. The system of claim 1, further comprising a capacitor coupled between the input and the base voltage.

7. The system of claim 1, further comprising a capacitor coupled between the output and the base voltage.

8. The system of claim 1, wherein the first set of switching devices includes:

a first switch which couples the higher potential terminal of the first capacitor to the input voltage during the first phase;

a second switch which couples the lower potential terminal of the first capacitor to the base voltage during the first phase;

a third switch which couples the higher potential terminal of the first capacitor to the output voltage during the second phase; and

a fourth switch which couples the lower potential terminal of the first capacitor to the input voltage during the second phase.

9. The system of claim 2, wherein the resonant clocking circuit is an LC oscillator circuit which includes at least two inductances and at least two capacitances.

10. The system of claim 9, wherein the resonant clocking circuit includes:

a first phase output;

a second phase output;

a first inductor coupled between a voltage source and the first phase output;

a second inductor coupled between the voltage source and the second phase output;

a first transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output; and

a second transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output.

11. The system of claim 1, wherein the first set of switching devices includes power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

12. The system of claim 1, wherein the first capacitor includes one or more ultra-low-ESR and ultra-low-ESL ceramic capacitors.

13. A method for converting a voltage, comprising:

receiving an input voltage through an input;

using a resonant clocking circuit to generate clock signals with substantially non-overlapping clock phases, including a first phase and a second phase;

applying the clock signals to a first set of switching devices which are configured to selectively couple a higher potential terminal and a lower potential terminal of a first capacitor between the input voltage, an output voltage and a base voltage, so that during the first phase the higher potential terminal of the first capacitor is coupled to the input voltage and the lower potential terminal of the first capacitor is coupled to the base voltage or lower, and during the second phase the higher potential terminal of the first capacitor is coupled to an output voltage and the lower potential terminal of the first capacitor is coupled to the input voltage;

applying the clock signals to a second set of switching devices which are configured to selectively couple a higher potential terminal and a lower potential terminal of a second capacitor between the input voltage, an output voltage and the base voltage, so that during the first phase the higher potential terminal of the second capacitor is coupled to the output voltage and the lower potential terminal of the second capacitor is coupled to the input voltage, and during the second phase the higher potential terminal of the second capacitor is coupled to the input voltage and the lower potential terminal of the second capacitor is coupled to the base voltage; and

providing the output voltage through an output.

14. The method of claim 13, wherein using the resonant clocking circuit to generate the clock signals involves using an LC oscillator to generate the clock signals.

15. The method of claim 13, wherein receiving the input voltage involves receiving the input voltage from a battery.

16. The method of claim 15, wherein receiving the input voltage involves receiving the input voltage from a battery which includes one or more battery cells which are coupled in parallel between the input and the base voltage.

17. The method of claim 13, further comprising using an output capacitor, which is coupled between the output and the base voltage.

18. The method of claim 13, further comprising using an input capacitor, which is coupled between the input and the base voltage.

19. The method of claim 14, further comprising using a capacitor, which is coupled between the input and the output.

20. The method of claim 13, wherein the first set of switching devices includes:

a first switch which couples the higher potential terminal of the first capacitor to the input voltage during the first phase;

a second switch which couples the lower potential terminal of the first capacitor to the base voltage during the first phase;

a third switch which couples the higher potential terminal of the first capacitor to the output voltage during the second phase; and

a fourth switch which couples the lower potential terminal of the first capacitor to the input voltage during the second phase.

21. The method of claim 13, wherein the resonant clocking circuit includes:

a first phase output;

a second phase output;

a first inductor coupled between a voltage source and the first phase output;

a second inductor coupled between the voltage source and the second phase output;

a first transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output; and

a second transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output.

22. The method of claim 13, wherein the first set of switching devices include power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

23. The method of claim 13, wherein the first capacitor includes one or more ultra-low-ESR and ultra-low ESL ceramic capacitors.

24. A power supply, comprising:

a battery that provides an input voltage;

an output that provides an output voltage;

a first and a second capacitor, each with a higher potential terminal and a lower potential terminal;

a first set of switching devices which selectively couple the higher potential and lower potential terminals of the first capacitor between the input voltage, the output voltage and a base voltage;

a second set of switching devices;

a resonant clocking circuit which generates clock signals with substantially non-overlapping clock phases, including a first phase and a second phase, for the first set of switching devices;

wherein the resonant clocking circuit is configured to control the first set of switching devices, so that during the first phase the higher potential terminal of the first capacitor is coupled to the input voltage and the lower potential terminal of the first capacitor is coupled to the base voltage, and during the second phase the higher potential terminal of the first capacitor is coupled to the output voltage and the lower potential terminal of the first capacitor is coupled to the input voltage; and

wherein the resonant clocking circuit is configured to control the second set of switching devices, so that during the first phase the higher potential terminal of the second capacitor is coupled to the output voltage and the lower potential terminal of the second capacitor is coupled to the input voltage, and during the second phase the higher potential terminal of the second capacitor is coupled to the input voltage and the lower potential terminal of the second capacitor is coupled to the base voltage.

25. The power supply of claim 24, wherein the resonant clocking circuit is an LC oscillator circuit which includes at least one inductance and at least one capacitance.

26. The power supply of claim 24, wherein the battery includes one or more battery cells which are coupled in parallel between the input and the base voltage.

27. The power supply of claim 24, further comprising an output capacitor coupled between the output and the base voltage.

28. The power supply of claim 24, further comprising an input capacitor coupled between the input and the base voltage.

29. The power supply of claim 24, further comprising a capacitor coupled between the output and the input.

30. The power supply of claim 24, wherein the first set of switching devices includes:

a first switch which couples the higher potential terminal of the first capacitor to the input voltage during the first phase;

a second switch which couples the lower potential terminal of the first capacitor to the base voltage during the first phase;

a third switch which couples the higher potential terminal of the first capacitor to the output voltage during the second phase; and

a fourth switch which couples the lower potential terminal of the first capacitor to the input voltage during the second phase.

31. The power supply of claim 24, wherein the resonant clocking circuit includes:

a first phase output;

a second phase output;

a first inductor coupled between a voltage source and the first phase output;

a second inductor coupled between the voltage source and the second phase output;

a first transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output; and

a second transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output.

32. The power supply of claim 24, wherein the first set of switching devices include power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

33. The power supply of claim 24, wherein the first capacitor includes one or more ultra-low-ESR and ultra-low ESL ceramic capacitors.