Static random access memory with data controlled power supply

• US 8,320,164 B2
• Filed: 01/05/2011
• Issued: 11/27/2012
• Est. Priority Date: 07/06/2010
• Status: Active Grant

• Current Assignee: Faraday Technology Corp., National Chiao Tung University (Government of The Republic of China)
• Original Assignee: Faraday Technology Corp., National Chiao Tung University (Government of The Republic of China)
• Inventors: Chuang, Ching-Te, Yang, Hao-I, Lin, Yung-Wei, Lu, Chien-Yu, Tu, Ming-Hsien, Hwang, Wei, Jou, Shyh-Jye, Chen, Chia-Cheng, Shih, Wei-Chiang, Hsia, Mao-Chih
• Primary Examiner(s): NGUYEN, DANG T
• Application Number:
  US12/985,289
• Publication Number:
  US 20120008377A1
• Time in Patent Office: 692 Days
• Field of Search: 365/154, 365/226, 365/189.16, 365/189.15, 365/189.11, 365/203, 365/230.05, 365/230.03, 365/189.06, 365/189.09, 365/189.07
• US Class Current: 365/154
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Claims

1. A static random access memory with data controlled power supply, comprising:

a memory cell circuit; and

at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit, comprising;

a first switch device, having a first terminal coupled to a first column-based Write word-line, a second terminal coupled to a first predetermined voltage level and a third terminal to provide the power to the memory cell circuit; and

a second switch device, having a first terminal coupled to a second column-based Write word-line, a second terminal coupled to the first predetermined voltage level and a third terminal to provide the power to the memory cell circuit.

2. The static random access memory of claim 1, wherein the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals respectively controlled by at least two switch devices.

3. The static random access memory of claim 1, wherein the Write-assist circuit comprises:

a power keeper, for providing currents to the memory cell circuit when the first switch device and the second switch device turn off.

4. The static random access memory of claim 3, wherein the power keeper comprises:

a third switch device, having a first terminal coupled to a ground level, a second terminal coupled to the third terminal of the first switch device, and a third terminal coupled to the first predetermined voltage level; and

a fourth switch device, having a first terminal coupled to a ground level, a second terminal coupled to the third terminal of the second switch device and a third terminal coupled to the first predetermined voltage level.

5. The static random access memory of claim 1, wherein the Write-assist circuit comprises:

a first inverter;

a second inverter;

a third switch device, having a first terminal coupled to the memory cell circuit, a second terminal coupled to the first column-based Write word-line via the first inverter, and a third terminal coupled to a ground level; and

a fourth switch device, having a first terminal coupled to the memory cell circuit, a second terminal coupled to the second column-based Write word-line via the second inverter, and a third terminal coupled to the ground level.

6. The static random access memory of claim 5, wherein the Write-assist circuit comprises:

a fifth switch device, having a first terminal coupled to the first terminal of the first switch device, a second terminal coupled to the third terminal of the third switch device, and a third terminal coupled to the first predetermined voltage level; and

a sixth switch device, having a first terminal coupled to the first terminal of the second switch device, a second terminal coupled to the third terminal of the fourth switch device, and a third terminal coupled to the first predetermined voltage level.

7. The static random access memory of claim 1, wherein the memory cell circuit comprises:

a latch circuit, having a first data-storage terminal and a second data-storage terminal, and having power receiving terminals to receive the power from the Write-assist circuit;

a third switch device, having a first bit transferring terminal coupled to the first data-storage terminal, a first control terminal coupled to the first column-based Write word-line, and a second bit transferring terminal;

a fourth switch device, having a third bit transferring terminal coupled to the second data-storage terminal, a second control terminal coupled to the second column-based Write word-line, and a fourth bit transferring terminal coupled to the second bit transferring terminal;

a fifth switch device, having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a row-based word-line, and a sixth bit transferring terminal coupled to a bit-line; and

a sensing amplifier, coupled to the bit-line, for determining a bit value appearing at the bit-line.

8. The static random access memory of claim 7, wherein the memory cell circuit further comprises:

a sixth switch device, having a control terminal coupled to the first data-storage terminal, a first terminal coupled to the fifth bit transferring terminal of the fifth switch device, and a second terminal coupled to a reference voltage level.

9. The static random access memory of claim 8, wherein the memory cell circuit further comprises:

a seventh switch device, having a first terminal coupled to the fifth bit transferring terminal of the fifth switch device, a second terminal coupled to the first terminal of the sixth switch device, and a control terminal coupled to the row-based word-line.

10. A static random access memory with data controlled power supply, comprising:

a memory cell circuit;

at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit;

a first switch device, having a first terminal coupled to the memory cell circuit, a second terminal coupled to the first column-based Write word-line via a first inverter coupled between the second terminal of the first switch device and the first column-based Write word-line, and a third terminal coupled to the first predetermined voltage level;

a second switch device, having a first terminal coupled to the memory cell circuit, a second terminal coupled to the second column-based Write word-line via a second inverter coupled between the second terminal of the second switch device and the second column-based Write word-line, and a third terminal coupled to the first predetermined voltage level;

a third switch device, having a first terminal coupled to the first predetermined voltage level, a second terminal coupled to the third terminal of the first switch device, and a third terminal coupled to the first terminal of the first switch device; and

a fourth switch device, having a first terminal coupled to the first switch device, a second terminal coupled to the third terminal of the second switch device, and a third terminal coupled to the first terminal of the second switch device.

11. A static random access memory with data controlled power supply, comprising:

a memory cell circuit; and

at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit, comprising;

a Write-Enable-Bar line;

a first logic circuit, coupled to the Write-Enable-Bar line and a bit-line to generate a first control signal;

a second logic unit, coupled to the Write-Enable-Bar line and the bit-line to generate a second control signal;

a first switch device, having a first terminal receiving the first control signal, a second terminal coupled to the first predetermined voltage level and a third terminal to provide the power to the memory cell circuit; and

a second switch device, having a first terminal receiving the second control signal, a second terminal coupled to the first predetermined voltage level and a third terminal to provide the power to the memory cell circuit.

12. The static random access memory of claim 11, wherein the Write-assist circuit comprises:

a power keeper, for providing currents to the memory cell circuit when the first switch device and the second switch device turn off.

13. The static random access memory of claim 12, further comprising:

a third switch device, having a first terminal coupled to a ground level, a second terminal coupled to the third terminal of the first switch device and a third terminal coupled to the first predetermined voltage level; and

a fourth switch device, having a first terminal coupled to a ground level, a second terminal coupled to the third terminal of the second switch device and a third terminal coupled to the first predetermined voltage level.

14. The static random access memory of claim 11, wherein the Write-assist circuit comprises:

a third logic circuit, coupled to the Write-Enable-Bar line and the bit-line to generate a third control signal; and

a third switch device, having a first terminal receiving the third control signal, a second terminal coupled to a ground voltage level and a third terminal coupled to the memory cell circuit.

15. The static random access memory of claim 14, wherein the Write-assist circuit comprises:

a power keeper, for providing currents to the memory cell circuit when the first switch device turns off.

16. The static random access memory of claim 15, wherein the power keeper comprises:

a fourth switch device, having a first terminal coupled to the first predetermined voltage level, a second terminal coupled to the ground voltage level, and a third terminal coupled to the third terminal of the third switch device.

17. The static random access memory of claim 11, wherein the memory cell circuit comprises:

a latch circuit, having a first data-storage terminal and a second data-storage terminal, and having power receiving terminals to receive the power from the Write-assist circuit;

a third switch device, having a first bit transferring terminal coupled to the first data-storage terminal, a first control terminal coupled to a first column-based word-line, and a second bit transferring terminal; and

a fourth switch device, having a third bit transferring terminal coupled to the second bit transferring terminal, a second control terminal coupled to a second row-based word-line, and a fourth bit transferring terminal coupled to a bit-line.

18. The static random access memory of claim 17, wherein the memory cell circuit further comprises:

a fifth switch device, having a control terminal coupled to the second data-storage terminal, a first terminal coupled to the third bit transferring terminal of the fourth switch device, and a second terminal coupled to a reference voltage level.

19. The static random access memory of claim 17, wherein the memory cell circuit further comprises:

a sixth switch device, having a control terminal coupled to the second row-based word-line, a first terminal coupled to the third bit transferring terminal of the second switch device, and a second terminal coupled to the first terminal of the fifth switch device.