Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

• US 8,320,191 B2
• Filed: 03/14/2008
• Issued: 11/27/2012
• Est. Priority Date: 08/30/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Strenz, Robert, Langheinrich, Wolfram, Roehrich, Mayk, Wiesner, Robert
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US12/049,132
• Publication Number:
  US 20090059678A1
• Time in Patent Office: 1,719 Days
• Field of Search: 365/185.18, 365/185.27, 365/185.28, 365/185.29
• US Class Current: 365/185.27
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Claims

1. A memory cell arrangement, comprising:

a substrate;

at least one memory cell, comprising a charge storing memory cell structure and a select structure;

a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well; and

a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well, wherein the control circuit comprises an erase circuit that is configured to provide at least one electric potential to the memory cell such that charge carriers stored in the charge storing memory cell structure are drained via at least the first doping well, wherein the erase circuit is configured to provide the same electric potential to the first, second and third doping wells.

2. The memory cell arrangement of claim 1, wherein the select structure comprises a select gate configured as a spacer and laterally disposed from a sidewall of the charge storing memory cell structure.

3. The memory cell arrangement of claim 1, wherein the erase circuit is configured to control the memory cell such that the charge storing memory cell structure is erased according to Fowler-Nordheim erase via at least the first doping well.

4. The memory cell arrangement of claim 1, further comprising at least one additional doping well arranged within the substrate, wherein the third doping well is arranged within the at least one additional doping well.

5. The memory cell arrangement of claim 1, wherein the charge storing memory cell structure is a non-volatile charge storing memory cell structure.

6. The memory cell arrangement of claim 5, wherein the charge storing memory cell structure is a floating gate memory cell structure or a charge trapping memory cell structure.

7. The memory cell arrangement of claim 1, wherein the control circuit comprises a program circuit that is configured to provide at least one electric potential to the memory cell such that charge carriers are introduced into the charge storing memory cell structure via at least the first doping well.

8. The memory cell arrangement of claim 7, wherein the program circuit is configured to control the memory cell such that the charge storing memory cell structure is programmed using a source side injection mechanism.

9. The memory cell arrangement of claim 1, further comprising:

a first wordline structure coupled with the memory cell and the erase circuit;

a second wordline structure coupled with another memory cell comprising another charge storing memory cell structure;

wherein the erase circuit is configured to provide a wordline inhibit voltage to the second wordline and thereby to the other charge storing memory cell structure when erasing the charge storing memory cell structure.

10. The memory cell arrangement of claim 9, wherein the wordline inhibit voltage is substantially equal to a voltage provided to at least one of the first, second and third doping wells.

11. The memory cell arrangement of claim 9, wherein the wordline inhibit voltage is lower than a voltage provided to at least one of the first, second and third doping wells.

12. An electronic device, comprising:

a logic arrangement comprising at least one logic device;

a memory cell arrangement, comprising;

a substrate;

at least one memory cell, comprising a charge storing memory cell structure and a select structure;

a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well; and

a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well, wherein the control circuit comprises an erase circuit that is configured to provide at least one electric potential to the memory cell such that charge carriers stored in the charge storing memory cell structure are drained via at least the first doping well, wherein the erase circuit is configured to provide the same electric potential to the first, second and third doping wells.

13. The electronic device of claim 12, wherein the select structure comprises a select gate configured as a spacer and laterally disposed from a sidewall of the charge storing memory cell structure.

14. The electronic device of claim 12, wherein the logic arrangement comprises at least one programmable logic device.

15. The electronic device of claim 12, wherein the control circuit is configured to control the memory cell such that the charge storing memory cell structure is erased according to Fowler-Nordheim erase via at least the first doping well.

16. The electronic device of claim 12, wherein the charge storing memory cell structure is a floating gate memory cell structure.

17. The electronic device of claim 12, configured as a smart card device.

18. A memory cell arrangement, comprising:

a substrate;

at least one memory cell comprising a charge storing memory cell structure and a select structure;

a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well;

a programming circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed by charging or discharging the charge storing memory cell structure via at least the first doping well; and

an erase circuit coupled with the memory cell and configured to provide at least one electric potential to the memory cell such that charge carriers stored in the charge storing memory cell structure are drained via at least the first doping well, wherein the erase circuit is configured to provide the same electric potential to the first, second and third doping wells.

19. The memory cell arrangement of claim 18, wherein the select structure comprises a select gate configured as a spacer and laterally disposed from a sidewall of the charge storing memory cell structure.

20. The memory cell arrangement of claim 18, wherein the erase circuit is configured to control the memory cell such that the charge storing memory cell structure is erased according to Fowler-Nordheim erase via at least the first doping well.

21. The memory cell arrangement of claim 18, wherein the charge storing memory cell structure is a floating gate memory cell structure or a charge trapping memory cell structure.

22. The memory cell arrangement of claim 18, wherein the program circuit is configured to control the memory cell such that the charge storing memory cell structure is programmed using a source side injection mechanism.

23. The memory cell arrangement of claim 18, further comprising:

a first wordline structure coupled with the memory cell and the erase circuit; and

a second wordline structure coupled with another memory cell comprising another charge storing memory cell structure;

wherein the erase circuit is configured to provide a wordline inhibit voltage to the second wordline when erasing the charge storing memory cell structure.

24. The memory cell arrangement of claim 23, wherein the wordline inhibit voltage is substantially equal to a voltage provided to at least one of the first, second and third doping wells.

25. The memory cell arrangement of claim 23, wherein the wordline inhibit voltage is lower than a voltage provided to at least one of the first, second and third doping wells.