Clocked memory system with termination component

• US 8,320,202 B2
• Filed: 06/25/2007
• Issued: 11/27/2012
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M.
• Application Number:
  US11/767,983
• Publication Number:
  US 20070247935A1
• Time in Patent Office: 1,982 Days
• Field of Search: 365/191, 365/194, 365/221, 365/198
• US Class Current: 365/191
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.

Claims

1. A system comprising:

a first memory device and a second memory device;

a first signal line coupled to the first memory device, the first signal line to provide first data, associated with a write command, to the first memory device;

a second signal line coupled to the second memory device, the second signal line to provide second data, associated with the write command, to the second memory device;

a termination component;

a control signal path coupled to the first memory device, the second memory device, and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component; and

a third signal line to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first memory device, wherein the clock signal also indicates when the write command propagating on the control signal path is to be sampled by the second memory device.

2. The system of claim 1, wherein the control signal path carries address information such that the address information propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component.

3. The system of claim 1, further comprising:

a memory controller coupled to the first memory device and the second memory device, the memory controller including;

timing circuitry to delay transmission of the first data to the first memory device by a first time interval that is based, at least in part, on an amount of time required for the write command propagating on the control signal path to propagate from the memory controller to the first memory device; and

timing circuitry to delay transmission of the second data to the second memory device by a second time interval that is based, at least in part, on an amount of time required for the write command propagating on the control signal path to propagate from the memory controller to the second memory device.

4. A system comprising:

a rank of memory device including a first memory device and a second memory device;

a first signal line coupled to the first memory device, the first signal line to provide first data, to be stored an array of the first memory device, in response to a write command;

a second signal line coupled to the second memory device, the second signal line to provide second data, to be stored in an array of the second memory device, in response to the write command;

a first termination component; and

a control signal path coupled to the first memory device, the second memory device, and the first termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component.

5. The system of claim 4, further comprising a third signal line to convey a timing signal that indicates a first time at which the write command propagating on the control signal path is to be sampled by the first memory device, wherein the timing signal also indicates a second time at which the write command propagating on the control signal path is to be sampled by the second memory device.

6. The system of claim 5, wherein the timing signal is a clock signal.

7. The system of claim 5, wherein the third signal line extends alongside the control signal path such that the timing signal propagates past each of the first memory device and the second memory device in the same order as the write command propagating on the control signal path.

8. The system of claim 4, further comprising:

a third signal line that extends alongside the first signal line, the third signal line to convey a first strobe signal that indicates a time at which the first data is to be sampled by the first memory device; and

a fourth signal line that extends alongside the second signal line, the fourth signal line to convey a second strobe signal that indicates a time at which the second data is to be sampled by the second memory device.

9. The system of claim 8, further comprising a memory controller coupled to the first signal line, second signal line and control signal path, the memory controller to provide the write command, wherein the memory controller includes:

first timing circuitry to delay transmission of the first data onto the first signal line by a time interval that is based, at least in part, on an amount of time required for the write command propagating on the control signal path to propagate from the memory controller to the first memory device; and

second timing circuitry to delay transmission of the second data onto the second signal line by a time interval that is based, at least in part, on an amount of time required for the write command propagating on the control signal path to propagate from the memory controller to the second memory device.

10. A system comprising:

a first memory device and a second memory device;

a first signal line coupled to the first memory device, the first signal line to provide first data, associated with a write command, to the first memory device;

a second signal line coupled to the second memory device, the second signal line to provide second data, associated with the write command, to the second memory device;

a control signal path coupled to the first memory device and the second memory device, such that the write command propagating on the control signal path propagates past the first memory device before reaching the second memory device; and

a third signal line to carry a clock signal that indicates a first time at which the write command propagating on the control signal path is to be sampled by the first memory device, wherein the timing signal also indicates a second time at which the write command propagating on the control signal path is to be sampled by the second memory device, wherein the third signal line extends alongside the control signal path such that the clock signal propagates past the first memory device and the second memory device in the same order as the write command propagating on the control signal path.

11. The system of claim 10, further comprising a memory controller coupled to the first signal line, second signal line and the control signal path, the memory controller to provide the write command, wherein the memory controller includes:

first timing circuitry to delay transmission of the first data onto the first signal line by a time interval that is based, at least in part, on an amount of time required for the write command propagating on the control signal path to propagate from the memory controller to the first memory device; and

second timing circuitry to delay transmission of the second data onto the second signal line by a time interval that is based, at least in part, on an amount of time required for the write command propagating on the control signal path to propagate from the memory controller to the second memory device.