Memory circuit and a tracking circuit thereof
First Claim
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1. A tracking circuit comprising:
- a dummy bit line;
a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal, wherein the wordline activation signal causes activation of a memory cell; and
a second circuit responsive to discharge of the dummy bit line to enable access to the memory cell;
wherein the first circuit comprises;
a third circuit to detect activation of a wordline and to generate the wordline activation signal in response to detection; and
a plurality of transistors in series connection to discharge the dummy bit line in response to the first signal and the wordline activation signal;
wherein the third circuit comprises;
an electrical line;
a first n-type metal oxide semiconductor (NMOS) transistor, having a gate coupled to the wordline and a drain coupled to the electrical line, to discharge the electrical line in response to the activation of the wordline; and
a fourth circuit to generate the wordline activation signal in response to the discharge of the electrical line.
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Abstract
Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.
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Citations
9 Claims
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1. A tracking circuit comprising:
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a dummy bit line; a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal, wherein the wordline activation signal causes activation of a memory cell; and a second circuit responsive to discharge of the dummy bit line to enable access to the memory cell; wherein the first circuit comprises; a third circuit to detect activation of a wordline and to generate the wordline activation signal in response to detection; and a plurality of transistors in series connection to discharge the dummy bit line in response to the first signal and the wordline activation signal; wherein the third circuit comprises; an electrical line; a first n-type metal oxide semiconductor (NMOS) transistor, having a gate coupled to the wordline and a drain coupled to the electrical line, to discharge the electrical line in response to the activation of the wordline; and a fourth circuit to generate the wordline activation signal in response to the discharge of the electrical line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification