Spread spectrum clock generator with controlled delay elements
First Claim
1. An integrated circuit comprising:
- a processor;
an input lead; and
a spread spectrum clock generator that receives a clock signal from the input lead and outputs a delayed clock signal to the processor,wherein the spread spectrum clock generator includes a programmable register storing programmable bits that are writable by the processor, wherein if a first digital logic value of the programmable bits is stored in the programmable register then the delayed clock signal has a substantially constant frequency, and wherein if a second digital logic value of the programmable bits is stored in the programmable register then the delayed clock signal has a variably dithered frequency.
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Accused Products
Abstract
A programmable spread spectrum clock generator (SSCG) reduces electromagnetic interference by spreading the frequency bandwidth of an output signal. The rate at which the frequency of the output signal changes, as well as other aspects of the output signal, are software programmable. The programmable SSCG receives a periodic signal whose cycles have substantially identical periods and outputs the output signal whose cycles have periods that vary smoothly over a plurality of cycles of the periodic signal. The programmable SSCG generates a control signal using the periodic signal. The programmable SSCG includes a variable delay element that generates the output signal by delaying the periods of the periodic signal based on the magnitude of the control signal. The output signal is generated without using a phase locked loop. Moreover, successive cycles of the output signal rarely have identical periods.
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Citations
19 Claims
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1. An integrated circuit comprising:
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a processor; an input lead; and a spread spectrum clock generator that receives a clock signal from the input lead and outputs a delayed clock signal to the processor, wherein the spread spectrum clock generator includes a programmable register storing programmable bits that are writable by the processor, wherein if a first digital logic value of the programmable bits is stored in the programmable register then the delayed clock signal has a substantially constant frequency, and wherein if a second digital logic value of the programmable bits is stored in the programmable register then the delayed clock signal has a variably dithered frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a processor; an oscillator that generates a periodic signal; and a spread spectrum clock generator that receives the periodic signal and outputs a delayed clock signal to the processor, wherein the spread spectrum clock generator includes a programmable spread spectrum control register storing slope control bits that are writable by the processor, wherein if a first digital value is stored in the slope control bits then the delayed clock signal has a substantially constant frequency, and wherein if a second digital value is stored in the slope control bits then the delayed clock signal has a variably dithered frequency. - View Dependent Claims (10, 11)
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12. A method comprising:
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receiving a periodic signal onto a spread spectrum clock generator that includes a programmable register storing programmable bits; delaying the periodic signal and thereby generating a delayed clock signal, wherein the delayed clock signal is generated without using a phase locked loop; writing a first digital logic value of the programmable bits to the programmable register; outputting the delayed clock signal from the spread spectrum clock generator, wherein the delayed clock signal has a substantially constant frequency when the programmable register contains the first digital logic value of the programmable bits; writing a second digital logic value of the programmable bits to the programmable register; and outputting the delayed clock signal from the spread spectrum clock generator, wherein the delayed clock signal has a variably dithered frequency when the programmable register contains the second digital logic value of the programmable bits. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification