System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system

• US 8,320,443 B2
• Filed: 04/28/2010
• Issued: 11/27/2012
• Est. Priority Date: 11/13/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Agazzi, Oscar E., Kruse, David, Abnous, Arthur, Hatamian, Mehdi
• Primary Examiner(s): Tran, Khanh C
• Application Number:
  US12/768,817
• Publication Number:
  US 20100208788A1
• Time in Patent Office: 944 Days
• Field of Search: 375232-233, 375/346, 375/348, 375/350, 370/286, 370290-291
• US Class Current: 375/233
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03458 Lattice
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03496 as a prediction filter
• CPC Class Codes: H04L 2025/03503 : as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 : Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03643 : Order recursive
• CPC Class Codes: H04L 2025/03745 : Timing of adaptation
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03203 : Trellis search techniques
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/03324 : Provision of tentative decisions
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter'"'"'s partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.

Claims

1. A receiver for demodulating an analog signal transmitted by a remote transmitter over a transmission channel, the analog signal including a first ISI (intersymbol interference) component induced by a characteristic of a pulse shaping filter included in the remote transmitter and a second ISI component induced by a characteristic of the transmission channel, the receiver comprising:

an analog front end, including an analog-to-digital converter, the analog front end receiving and converting the analog signal to a first digital signal;

an equalizer block coupled to the analog front end to receive the first digital signal, the equalizer block compensating the first ISI component in the first digital signal and outputting a second digital signal; and

a decision feedback sequence estimation block, including an ISI compensation circuit, the ISI compensation circuit receiving the second digital signal outputted by the equalizer block and compensating the second ISI component in the second digital signal.

2. The receiver of claim 1 wherein the equalizer block comprises:

an ISI compensation filter having an impulse response substantially inverse of the impulse response of the pulse shaping filter of the remote transmitter; and

an adaptive gain stage coupled to a summing device at an input of the adaptive gain stage, wherein the summing device subtracts at least one signal received from an offset canceler, a near-end crosstalk canceler, or an echo canceler from an output signal of the ISI compensation filter to form an input signal to the adaptive gain stage.

3. The receiver of claim 2 wherein the ISI compensation filter is an inverse partial response filter.

4. The receiver of claim 3 wherein the equalizer block is configured as a feedforward equalizer.

5. The receiver of claim 1 wherein the decision feedback sequence estimation block comprises:

a decoder block receiving and decoding at least one ISI compensated signal sample, and generating tentative decisions and a final decision; and

a decision feedback equalizer coupled in feedback fashion to the decoder block, the decision feedback equalizer including a set of low-ordered coefficients and a set of high-ordered coefficients, the decision feedback equalizer generating a first portion of ISI compensation for the second ISI component based on the tentative decisions and the high-ordered coefficients.

6. The receiver of claim 5 wherein the decision feedback sequence estimation block further comprises a convolution engine coupled to the decision feedback equalizer to receive values of the low-ordered coefficients, the convolution engine computing a set of pre-computed values representing a set of potential second ISI compensation portions for the second ISI component.

7. The receiver of claim 6 wherein the second digital signal is combined with the first portion of ISI compensation to produce a third digital signal partially compensated for the second ISI component.

8. The receiver of claim 7 wherein the decision feedback sequence estimation block further comprises a multiple decision feedback equalizer coupled to the decision feedback equalizer and the convolution engine, the multiple decision feedback equalizer combining the set of pre-computed values with the third digital signal to produce a set of potential digital signals, one of the potential digital signals being substantially compensated for the second ISI component.

9. The receiver of claim 8 wherein the multiple decision feedback equalizer includes a multiplexer, the multiplexer receiving the set of potential digital signals, selecting one of the potential digital signals based on at least one tentative decision received from the decoder block, and providing the selected one of the potential digital signals to the decoder block as the at least one ISI compensated signal sample.

10. A method for demodulating an analog signal transmitted by a remote transmitter over a transmission channel, the analog signal including a first ISI (intersymbol interference) component induced by a characteristic of a pulse shaping filter included in the remote transmitter and a second ISI component induced by a characteristic of the transmission channel, the method comprising the operations of:

(a) receiving the analog signal in an analog front end;

(b) converting the analog signal to a first digital signal;

(c) compensating the first ISI component included in the first digital signal using an equalizer block;

(d) producing a second digital signal, the second digital signal being substantially equal to the first digital signal with the first ISI component substantially compensated;

(e) compensating the second ISI component included in the second digital signal;

(f) producing a third digital signal, the third digital signal being substantially equal to the second digital signal with the second ISI component substantially compensated; and

(g) decoding the third digital signal.

11. The method according to claim 10 wherein operation (c) comprises the operations of:

filtering the first digital signal using an ISI compensation filter, the ISI compensation filter having an impulse response substantially inverse of the impulse response of the pulse shaping filter of the remote transmitter; and

adjusting a gain of the filtered first digital signal using an adaptive gain stage.

12. The method according to claim 11 wherein the ISI compensation filter is an inverse partial response filter.

13. The method according to claim 12 wherein the equalizer block is configured as a feedforward equalizer.

14. The method according to claim 10 wherein operation (g) comprises:

generating tentative decisions from a decoder block; and

combining tentative decisions with values of a set of high-ordered coefficients in a decision feedback equalizer to generate a first portion of ISI compensation for the second ISI component.

15. The method according to claim 14 wherein operation (e) comprises:

defining a set of low-order coefficients from the decision feedback equalizer combining the set of low-order coefficients with a set of values representing levels of a multi-level alphabet so as to generate a set of pre-computed values representing a set of potential second portions of ISI compensation for the second ISI component.

16. The method according to claim 15 wherein operation (e) further comprises the operation of combining the first portion of ISI compensation to the second digital signal to generate an intermediate digital signal having the first ISI component substantially compensated and the second ISI component partially compensated.

17. The method according to claim 16 wherein operation (e) further comprises the operation of combining the set of pre-computed values with the intermediate digital signal to define a set of potential digital signals, one of the potential digital signals being substantially compensated for both the first and the second ISI components.

18. The method according to claim 17 wherein operation (e) further comprises:

selecting one of the potential digital signals based on at least one tentative decision received from the decoder block, the selected one of the potential digital signals being the third digital signal.

19. A receiver for demodulating an analog signal transmitted by a remote transmitter over a transmission channel, the analog signal including a first ISI (intersymbol interference) component induced by a characteristic of a pulse shaping filter included in the remote transmitter and a second ISI component induced by a characteristic of the transmission channel, the receiver comprising:

an analog front end including an analog-to-digital converter, the analog front end receiving the analog signal and outputting a first digital signal;

a first ISI compensation circuit receiving the first digital signal from the analog front end and outputting a second digital signal, the second digital signal being substantially compensated for the first ISI component; and

a second ISI compensation circuit, the second ISI compensation circuit receiving the second digital signal and generating a third digital signal, the third digital signal being substantially compensated for the second ISI component.

20. The receiver according to claim 19 wherein the first ISI compensation circuit comprises:

an inverse partial response filter; and

wherein the inverse partial response filter has an impulse response substantially inverse of the impulse response of the pulse shaping filter of the remote transmitter, so as to substantially compensate the first digital signal for the first ISI component.

21. The receiver according to claim 20 wherein the inverse partial response filter is implemented with a characteristic feedback gain factor K.

22. The receiver according to claim 21 wherein the inverse partial response filter operates in accordance with a non-zero value of the characteristic feedback gain factor K during communication initialization and wherein the value of the feedback gain factor K is ramped down to zero after a pre-defined interval.

23. The receiver according to claim 22 wherein the second ISI compensation circuit further comprises:

a Viterbi decoder configured to decode the third digital signal and generate tentative decisions; and

feedback equalizer circuitry coupled to the Viterbi decoder, the feedback equalizer circuitry receiving the tentative decisions and combining the tentative decisions with a set of high-ordered coefficients to generate a first value.

24. The receiver according to claim 23 wherein the second ISI compensation circuit further comprises:

summing circuitry combining the first value with the second digital signal, the summing circuitry outputting an intermediate signal; and

a multiple decision feedback equalizer receiving the intermediate signal and combining the intermediate signal with a set of pre-computed values generated by combining values of a set of low-ordered coefficients with a set of values representing levels of a multi-level symbolic alphabet to produce a set of potential digital signals, one of the potential digital signals being substantially ISI compensated the multiple decision feedback equalizer outputting said one of the potential digital signals to the Viterbi decoder.

25. The receiver according to claim 24, wherein the feedback equalizer circuitry is a decision feedback equalizer having a multiplicity of coefficients, the low-ordered coefficients comprising the first two coefficients of the multiplicity of coefficients.

26. The receiver according to claim 25 wherein the high-ordered coefficients comprise the remaining coefficients of the multiplicity of coefficients.

27. The receiver according to claim 26, wherein the characteristic feedback gain factor K is ramped to zero after 20 convergence of the decision feedback equalizer.

28. The receiver according to claim 19 wherein the receiver is included in an integrated circuit transceiver.