Method and system for single chip satellite set-top box system

• US 8,320,822 B2
• Filed: 09/27/2011
• Issued: 11/27/2012
• Est. Priority Date: 07/11/2003
• Status: Expired due to Term

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bushner, Paige
• Primary Examiner(s): LE, NHAN T
• Application Number:
  US13/246,599
• Publication Number:
  US 20120066725A1
• Time in Patent Office: 427 Days
• Field of Search: 455/3.02, 455/101, 455/132, 455/133, 455/137, 455/313, 455/314, 455/323, 455/324, 455/333, 342/357.01, 342/357.06, 342/357.12, 701/213, 701/214, 701/215
• US Class Current: 455/3.02
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/42684 Client identification by a unique number or address, e.g. serial number, MAC address, socket ID network arrangements, protocols or services for addressing or naming H04L61/00

Abstract

A system for processing signals includes a single integrated circuit chip that includes one or more circuits, the one or more circuits including a first receiver demodulator and a second receiver demodulator. The one or more circuits are operable to: control access to information received by one or both of the first demodulator and/or the second receiver demodulator utilizing at least one secure key stored in on-chip memory within the single integrated circuit chip; and generate an audio stream and a video stream based on one or both of the information received by the first receiver demodulator and/or the information received by the second receiver demodulator. The one or more circuits include one or more video decoders, one or more video and graphics display engines coupled to the one or more video decoders; and one or more video encoders coupled to the one or more video and graphics display engines.

Claims

1. A system for processing signals, the system comprising:

a single integrated circuit chip, comprising one or more circuits, said one or more circuits comprising a first receiver demodulator and a second receiver demodulator, wherein said one or more circuits are operable to;

control access to information received by one or both of said first demodulator or said second receiver demodulator utilizing at least one secure key stored in on-chip memory within said single integrated circuit chip; and

generate an audio stream and a video stream based on one or both of said information received by said first receiver demodulator or said information received by said second receiver demodulator.

2. The system according to claim 1, wherein said one or more circuits comprises:

one or more video decoders coupled to said one or more processors;

one or more video and graphics display engines coupled to said one or more video decoders; and

one or more video encoders coupled to said one or more video and graphics display engines.

3. The system according to claim 2, comprising one or more video digital-to-analog converters and one or more RF modulators integrated within said single integrated circuit chip, and said one or more video digital-to-analog converters and said one or more RF modulators are coupled to said one or more video encoders.

4. The system according to claim 2, wherein said one or more video decoders comprises a standard definition MPEG-2 video decoder.

5. The system according to claim 1, comprising one or more audio decoders integrated within said single integrated circuit chip, wherein said one or more audio decoders are coupled to said one or more processors.

6. The system according to claim 5, wherein said one or more audio decoders comprises an MPEG-2 audio decoder.

7. The system according to claim 5, comprising one or more audio digital-to-analog converters integrated within said single integrated circuit chip, wherein said one or more audio digital-to-analog converters are coupled to said one or more audio decoders.

8. The system according to claim 1, comprising one or more memory controllers integrated within said single integrated circuit chip, wherein said one or more memory controllers are coupled to at least said one or more processors.

9. The system according to claim 8, wherein said one or more memory controllers comprises a unified dual data rate DRAM memory controller.

10. The system according to claim 1, comprising a digital satellite equipment control (DiSEqC) bus integrated within said single integrated circuit chip.

11. The system according to claim 1, comprising one or more of a plurality of peripheral interfaces comprising, an infrared interface, a universal asynchronous receiver/transmitter, a serial peripheral interface, a binary synchronous communication interface, general purpose input/output pins, and/or pulse width modulation controller interface, integrated within said single integrated circuit chip.

12. The system according to claim 1, comprising one or more read-only memory integrated within said single integrated circuit chip.

13. The system according to claim 12, wherein said one or more read-only memory comprises a CPU boot ROM and a FLASH.

14. The system according to claim 1, comprising one or more debug ports integrated within said single integrated circuit chip.

15. The system according to claim 14, wherein said debug port comprises a JTAG port or any variation thereof.

16. The system according to claim 1, comprising card reader, card writer interfaces, or a combination thereof integrated within said single integrated circuit chip.

17. The system according to claim 16, wherein said card reader, card writer interfaces, or combination thereof comprises a smart card reader, a smart card writer interface, or combination thereof.

18. The system according to claim 1, comprising one or more core voltage regulators integrated within said single integrated circuit chip.

19. The system according to claim 1, comprising one or more phase lock loops integrated within said single integrated circuit chip.

20. The system according to claim 1, comprising one or more telephony modems integrated within said single integrated circuit chip.

21. The system according to claim 1, wherein said first receiver demodulator and said second receiver demodulator comprise an 8 PSK, 8 PSK-turbo, or QPSK demodulators, or combination thereof.

22. A system for processing signals, the system comprising:

a single integrated circuit chip, comprising one or more circuits, said one or more circuits comprising a first receiver demodulator, a second receiver demodulator, one or more video decoders, and one or more audio decoders, wherein said one or more circuits are operable to;

control access to information received by one or both of said first demodulator or said second receiver demodulator utilizing at least one secure key stored in on-chip memory within said single integrated circuit chip; and

generate an audio stream and a video stream based said one or both of said information received by said first receiver demodulator or said information received by said second receiver demodulator, using said one or more video decoders, said one or more audio decoders, or a combination thereof.

23. The system according to claim 22, wherein said one or more circuits comprises:

one or more video and graphics display engines coupled to said one or more video decoders; and

one or more video encoders coupled to said one or more video and graphics display engines.

24. The system according to claim 23, wherein said one or more circuits comprises one or more video digital-to-analog converters and one or more RF modulators, and said one or more video digital-to-analog converters and said one or more RF modulators are coupled to said one or more video encoders.

25. The system according to claim 23, wherein said one or more video decoder comprises a standard definition MPEG-2 video decoder.

26. The system according to claim 22, wherein said one or more audio decoders are coupled to said one or more processors.

27. The system according to claim 26, wherein said one or more audio decoders comprises an MPEG-2 audio decoder.

28. The system according to claim 26, wherein said one or more circuits comprises one or more audio digital-to-analog converters, and said one or more audio digital-to-analog converters are coupled to said one or more audio decoders.

29. The system according to claim 22, wherein said one or more circuits comprises one or more memory controllers, and said one or more memory controllers are coupled to at least said one or more processors.

30. The system according to claim 29, wherein said one or more memory controllers comprises a unified dual data rate DRAM memory controller.

31. The system according to claim 22, wherein said one or more circuits comprises a digital satellite equipment control (DiSEqC) bus.

32. The system according to claim 22, wherein said one or more circuits comprises one or more of a plurality of peripheral interfaces comprising an infrared interface, a universal asynchronous receiver/transmitter, a serial peripheral interface, a binary synchronous communication interface, general purpose input/output pins, or pulse width modulation controller interface.

33. The system according to claim 22, wherein said one or more circuits comprises one or more read-only memory.

34. The system according to claim 33, wherein said one or more read-only memory comprises a CPU boot ROM and a FLASH.

35. The system according to claim 22, wherein said one or more circuits comprises one or more debug ports.

36. The system according to claim 35, wherein said debug port comprises a JTAG port or any variation thereof.

37. The system according to claim 22, wherein said one or more circuits comprises a card reader, card writer interfaces, or combination thereof integrated within said single integrated circuit chip.

38. The system according to claim 37, wherein said card reader, card writer interfaces, or combination thereof comprises a smart card reader, a smart card writer interface, or combination thereof.

39. The system according to claim 22, wherein said one or more circuits comprises one or more core voltage regulators.

40. The system according to claim 22, wherein said one or more circuits comprises one or more phase lock loops.

41. The system according to claim 22, wherein said one or more circuits comprises one or more telephony modems.

42. The system according to claim 22, wherein one or both of said first receiver demodulator and said second receiver demodulator comprise a 8 PSK, 8 PSK-turbo, or QPSK demodulators, or combination thereof.

43. A method for processing information, the method comprising:

performing by one or more processors, circuits, or combination thereof within a single integrated circuit chip;

receiving a first modulated signal by a first receiver integrated within said single integrated circuit chip;

demodulating said first modulated signal by said first receiver to generate a first demodulated signal;

receiving a second modulated signal by a second receiver integrated within said single integrated circuit chip;

demodulating said second modulated signal by said second receiver to generate a second demodulated signal, wherein access to information received by said first and said second receiver demodulators is controlled using at least one secure key stored in on-chip memory within said single integrated circuit chip;

decoding a video portion of said second demodulated signal to generate a second decoded video signal;

encoding said second decoded video signal to generate a second encoded digital video signal; and

converting said second encoded digital video signal to a second analog video signal.

44. The method according to claim 43, wherein said demodulating of said first modulated signal and said demodulating of said second modulated signal occurs concurrently.

45. The method according to claim 43, comprising decoding by said one or more processors, circuits, or combination thereof, a video portion of said first demodulated signal to generate a first decoded video signal.

46. The method according to claim 45, comprising encoding by said one or more processors, circuits, or combination thereof, said first decoded video signal to generate a first encoded digital video signal.

47. The method according to claim 46, comprising converting by said one or more processors, circuits, or combination thereof, said first encoded digital video signal to a first analog video signal.

48. The method according to claim 43, comprising decoding by said one or more processors, circuits, or combination thereof, an audio portion of said first demodulated signal to generate a first decoded digital audio signal.

49. The method according to claim 48, comprising converting by said one or more processors, circuits, or combination thereof, said first decoded digital audio signal to a first analog audio signal.

50. A method for processing information, the method comprising:

performing by one or more processors, circuits, or combination thereof within a single integrated circuit chip;

receiving a first modulated signal by a first receiver;

demodulating said first modulated signal by said first receiver to generate a first demodulated signal;

receiving a second modulated signal by a second receiver;

demodulating said second modulated signal by said second receiver to generate a second demodulated signal, wherein access to information received by said first and said second receiver demodulators is controlled using at least one secure key stored in on-chip memory within said single integrated circuit chip;

decoding a video portion of said second demodulated signal to generate a second decoded video signal;

decoding an audio portion of said second demodulated signal to generate a second decoded digital audio signal; and

converting said second decoded digital audio signal to a second analog audio signal.

51. The method according to claim 50, wherein said demodulating of said first modulated signal and said demodulating of said second modulated signal occurs simultaneously.

52. The method according to claim 51, comprising decoding by said one or more processors, circuits, or combination thereof, a video portion of said first demodulated signal to generate a first decoded video signal.

53. The method according to claim 52, comprising encoding by said one or more processors, circuits, or combination thereof, said first decoded video signal within said single integrated circuit chip to generate a first encoded digital video signal.

54. The method according to claim 53, comprising converting by said one or more processors, circuits, or combination thereof, said first encoded digital video signal to a first analog video signal.

55. The method according to claim 50, comprising decoding by said one or more processors, circuits, or combination thereof, an audio portion of said first demodulated signal to generate a first decoded digital audio signal.

56. The method according to claim 55, comprising converting by said one or more processors, circuits, or combination thereof, said first decoded digital audio signal to a first analog audio signal.