Method and system for multiple tuner application using a low noise broadband distribution amplifier

• US 8,320,864 B2
• Filed: 07/15/2009
• Issued: 11/27/2012
• Est. Priority Date: 08/15/2001
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Fanous, Adel, Dauphinee, Leonard, Burns, Lawrence M., McMullin, Donald
• Primary Examiner(s): Nguyen, Simon
• Application Number:
  US12/503,232
• Publication Number:
  US 20090273401A1
• Time in Patent Office: 1,231 Days
• Field of Search: 455/132, 455/136, 455/138, 455/189, 455/232.1, 4552341-2342, 455/239.1, 455/240.1, 4552451-2511, 455/241.1, 455/253.2, 455/341, 375/345, 330/124.R, 330/278, 330/295
• US Class Current: 455/232.1
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 2203/45311 the common gate stage of a cascode dif amp being implemented by multiple transistors
• CPC Class Codes: H03F 2203/45464 the CSC comprising one or more coils
• CPC Class Codes: H03F 2203/45466 the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45696 the LC comprising more than two resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45201 Non-folded cascode stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence

Abstract

An active splitter circuit arrangement includes a first amplification module having a number of first input ports and first output ports. The first amplification module is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals, each substantially matching the input signal. Also included is a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports. The first gain control device is configured to control a gain of the first amplification module. Next, a number of second amplification modules corresponding to the number of output signals has a number of second input ports respectively coupled to the first output ports. Each second amplification module is configured to receive a control signal from the second gain control device, provide second stage amplification to a corresponding one of the number of output signals based upon the control signal and produce an amplified output signal.

Claims

1. An amplifier comprising:

a first amplification module having a number of first input ports and first output ports, the first amplification module being configured to (i) provide first stage amplification to a received input signal and (ii) produce from the amplified input signal a number of output signals, each having characteristics substantially matching characteristics of the input signal;

a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports, the first gain control device being configured to control a gain of the first amplification module; and

a number of second amplification modules, each having a number of second input ports respectively coupled to the first output ports;

wherein each second amplification module is configured to (i) receive a control signal from a second gain control device, (ii) provide second stage amplification to a corresponding one of the number of output signals based upon the control signal and (iii) produce an amplified output signal.

2. The amplifier of claim 1, wherein each amplified output signal is a differential signal.

3. The amplifier of claim 2, wherein the first amplification module is a low noise amplifier.

4. The amplifier of claim 2, wherein the first amplification module is a low noise variable gain amplifier.

5. The amplifier of claim 2, wherein the first gain control device simultaneously controls a gain of all of the number of second amplification modules.

6. The amplifier of claim 2, wherein the number of output signals is representative of a predetermined frequency spectrum;

and

wherein the first gain control device simultaneously controls a gain across the predetermined frequency spectrum.

7. The amplifier of claim 2, wherein a gain of the first amplification module is digitally controlled.

8. The amplifier of claim 2, wherein the first amplification module comprises:

a power detector configured to (i) monitor the first output ports, (ii) produce a compensating signal based upon the monitoring, and (iii) provide the compensating signal as an input to the first amplification module.

9. The amplifier of claim 1, further comprising:

a tuner coupled to each of the second stage amplification modules and configured to receive the amplified output signal;

wherein the tuner derives information from the amplified output signal based upon a predetermined operating frequency, the tuner producing a tuned signal thereby; and

a demodulator coupled to the tuner and configured to demodulate the tuned signal, the demodulator (i) producing a gain control signal and (ii) providing the gain control signal to the second gain control device.

10. The amplifier of claim 9, wherein the first and second amplification modules are differential amplifiers.

11. The amplifier of claim 9, wherein the tuner comprises:

a variable gain amplifier.

12. The amplifier of claim 9, wherein the tuner comprises:

a number of mixers and at least one filter.

13. The amplifier of claim 12, wherein the filter is configured to have a bandwidth comprising:

five or fewer channels.

14. The amplifier of claim 12, wherein the first amplification module comprises:

a pair of plural differential amplifiers and a dividing network.

15. The amplifier of claim 14, wherein a gain of the first amplification module is controlled by selectively activating or deactivating particular ones of the plural differential amplifiers of the pair.

16. The amplifier of claim 14, wherein the filter is configured to have a bandwidth comprising:

five or fewer channels.