Source core interrupt steering
First Claim
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1. A method comprising:
- receiving a core identifier that corresponds with a source core, wherein the source core is included in a processor;
receiving an input/output request, produced from the source core, that is associated with the core identifier;
storing the core identifier in a memory coupled to the processor;
directing an interrupt, which corresponds to the request, to the source core based on the core identifier;
receiving an additional core identifier that corresponds with the source core;
receiving an additional input/output request, produced from the source core, that is associated with the additional core identifier; and
coalescing the request and additional request based on an affiliation between the core identifier and the additional core identifier;
wherein the processor is coupled to an additional core and the request includes the core identifier.
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Abstract
An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.
8 Citations
18 Claims
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1. A method comprising:
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receiving a core identifier that corresponds with a source core, wherein the source core is included in a processor; receiving an input/output request, produced from the source core, that is associated with the core identifier; storing the core identifier in a memory coupled to the processor; directing an interrupt, which corresponds to the request, to the source core based on the core identifier; receiving an additional core identifier that corresponds with the source core; receiving an additional input/output request, produced from the source core, that is associated with the additional core identifier; and coalescing the request and additional request based on an affiliation between the core identifier and the additional core identifier; wherein the processor is coupled to an additional core and the request includes the core identifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An article comprising a medium storing instructions that enable a processor-based system to:
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receive a core identifier (CID) that corresponds with a source core, wherein the source core is included in a processor; receive an input/output request, produced from the source core, that is associated with the core identifier; store the CID in a memory coupled to the processor; direct an interrupt, which corresponds to the request, to the source core based on the core identifier; receive an additional core identifier that corresponds with the source core; receive an additional input/output request, produced from the source core, that is associated with the additional core identifier; and coalesce the request and additional request based on an affiliation between the core identifier and the additional core identifier; wherein the processor is coupled to an additional core and the request includes the CID. - View Dependent Claims (11, 12, 13)
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14. A method comprising:
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using a first queue identifier (QID) to associate a first controller request queue with a first processor core; using a second QID to associate a second controller request queue with a second processor core; storing a first input/output (I/0) request, which is produced from the first core and is associated with the first QID, in the first queue based on the first QID; and directing a first interrupt, which corresponds to the first request, to one of the first and second cores based on the first QID. - View Dependent Claims (15, 16, 17, 18)
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Specification