Semiconductor device having a threshold voltage control function

• US 8,321,711 B2
• Filed: 06/29/2011
• Issued: 11/27/2012
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US13/171,549
• Publication Number:
  US 20110255326A1
• Time in Patent Office: 517 Days
• Field of Search: None
• US Class Current: 713/323
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components

Abstract

The invention provides a semiconductor device that power is stabilized by suppressing power consumption as much as possible. The semiconductor device of the invention includes a logic portion and a memory portion each including a plurality of transistors, a detecting portion for detecting one or both of operation frequencies of the logic portion and the memory portion, a Vth control for supplying a Vth control signal to one or both of the logic portion and the memory portion, and an antenna. Each of the plurality of transistors has a first gate electrode which is input with a logic signal, a second gate electrode which is input with the Vth control signal, and a semiconductor film such that the second gate electrode, the semiconductor film, and the first gate electrode are provided in this order from the bottom.

Claims

1. A semiconductor device comprising:

a first portion;

a second portion;

a third portion configured to detect an operation frequency of the first portion or an operation frequency of the second portion;

a fourth portion configured to supply a Vth control signal to the first portion or the second portion depending on a detection result from the third portion; and

a wiring electrically connected to the first portion,

wherein each of the first portion and the second portion comprises at least one transistor,

wherein the at least one transistor has a first gate electrode which is input with a first signal and a second gate electrode which is input with the Vth control signal, and

wherein at least the first portion is provided with electric power from the wiring.

2. The semiconductor device according to claim 1, wherein the first portion includes a logic circuit, and

wherein the second portion includes a memory circuit.

3. The semiconductor device according to claim 1,

wherein the first portion comprises more than one of a control circuit, an arithmetic circuit, an input/output circuit, a power source circuit, a clock generating circuit, a data demodulation/modulation circuit, and an interface circuit.

4. The semiconductor device according to claim 1,

wherein the first portion comprises a timing control, an instruction decoder, a register array, an address logic and buffer, a data bus interface, an ALU (Arithmetic Logic Unit), and an instruction register.

5. The semiconductor device according to claim 1, wherein the second portion comprises one or more of a DRAM, an SRAM, an FeRAM, a masked ROM, a fuse PROM, an anti-fuse PROM, EPROM, an EEPROM, and a flash memory.

6. The semiconductor device according to claim 1, wherein the third portion is a program or a storage medium storing the program.

7. A semiconductor device comprising:

a first portion;

a second portion;

a detecting portion for detecting at least one of an operation frequency of the first portion and an operation frequency of the second portion;

a Vth control portion for supplying a Vth control signal to at least one of the first portion and the second portion depending on a detection result from the detecting portion; and

a wiring electrically connected to the first portion,

wherein each of the first portion and the second portion comprises at least one transistor,

wherein the at least one transistor has a first gate electrode which is input with a first signal and a second gate electrode which is input with the Vth control signal, and

wherein at least the first portion is provided with electric power from the wiring.

8. The semiconductor device according to claim 7, wherein the first portion includes a logic circuit, and

wherein the second portion includes a memory circuit.

9. The semiconductor device according to claim 7,

wherein the first portion comprises more than one of a control circuit, an arithmetic circuit, an input/output circuit, a power source circuit, a clock generating circuit, a data demodulation/modulation circuit, and an interface circuit.

10. The semiconductor device according to claim 7,

wherein the first portion comprises a timing control, an instruction decoder, a register array, an address logic and buffer, a data bus interface, an ALU (Arithmetic Logic Unit), and an instruction register.

11. The semiconductor device according to claim 7,

wherein the second portion comprises one or more of a DRAM, an SRAM, an FeRAM, a masked ROM, a fuse PROM, an anti-fuse PROM, EPROM, an EEPROM, and a flash memory.

12. The semiconductor device according to claim 7, wherein the detecting portion is a program or a storage medium storing the program.

13. A semiconductor device comprising:

a first portion;

a second portion;

a third portion configured to detect an operation frequency of the first portion or an operation frequency of the second portion;

a fourth portion configured to supply a Vth control signal to the first portion or the second portion depending on a detection result from the third portion; and

a wiring electrically connected to the first portion,

wherein each of the first portion and the second portion comprises at least one transistor,

wherein the at least one transistor has a first gate electrode which is input with a first signal and a second gate electrode which is input with the Vth control signal, and a semiconductor film,

wherein the semiconductor film is provided over the second gate electrode,

wherein the first gate electrode is provided over the semiconductor film, and

wherein at least the first portion is provided with electric power from the wiring.

14. The semiconductor device according to claim 13, wherein the first portion includes a logic circuit, and

wherein the second portion includes a memory circuit.

15. The semiconductor device according to claim 13,

wherein the first portion comprises more than one of a control circuit, an arithmetic circuit, an input/output circuit, a power source circuit, a clock generating circuit, a data demodulation/modulation circuit, and an interface circuit.

16. The semiconductor device according to claim 13,

wherein the first portion comprises a timing control, an instruction decoder, a register array, an address logic and buffer, a data bus interface, an ALU (Arithmetic Logic Unit), and an instruction register.

17. The semiconductor device according to claim 13,

wherein the second portion comprises one or more of a DRAM, an SRAM, an FeRAM, a masked ROM, a fuse PROM, an anti-fuse PROM, EPROM, an EEPROM, and a flash memory.

18. The semiconductor device according to claim 13, wherein the third portion is a program or a storage medium storing the program.

19. A semiconductor device comprising:

a first portion;

a second portion;

a detecting portion for detecting at least one of an operation frequency of the first portion and an operation frequency of the second portion;

a Vth control portion for supplying a Vth control signal to at least one of the first portion and the second portion depending on a detection result from the detecting portion; and

a wiring electrically connected to the first portion,

wherein each of the first portion and the second portion comprises at least one transistor,

wherein the at least one transistor has a first gate electrode which is input with a first signal and a second gate electrode which is input with the Vth control signal, and a semiconductor film,

wherein the semiconductor film is provided over the second gate electrode,

wherein the first gate electrode is provided over the semiconductor film, and

wherein at least the first portion is provided with electric power from the wiring.

20. The semiconductor device according to claim 19, wherein the first portion includes a logic circuit, and

wherein the second portion includes a memory circuit.

21. The semiconductor device according to claim 19,

wherein the first portion comprises more than one of a control circuit, an arithmetic circuit, an input/output circuit, a power source circuit, a clock generating circuit, a data demodulation/modulation circuit, and an interface circuit.

22. The semiconductor device according to claim 19,

wherein the first portion comprises a timing control, an instruction decoder, a register array, an address logic and buffer, a data bus interface, an ALU (Arithmetic Logic Unit), and an instruction register.

23. The semiconductor device according to claim 19,

wherein the second portion comprises one or more of a DRAM, an SRAM, an FeRAM, a masked ROM, a fuse PROM, an anti-fuse PROM, EPROM, an EEPROM, and a flash memory.

24. The semiconductor device according to claim 19, wherein the detecting portion is a program or a storage medium storing the program.