Integrated circuit having frequency dependent noise avoidance

• US 8,321,716 B2
• Filed: 06/08/2010
• Issued: 11/27/2012
• Est. Priority Date: 07/26/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US12/796,533
• Publication Number:
  US 20100250997A1
• Time in Patent Office: 903 Days
• Field of Search: 713/500, 713/600, 331/1.R, 331/46, 326/93, 327/100, 375/316, 375/354, 455/130
• US Class Current: 713/500
• CPC Class Codes: H04B 15/06 by local oscillators of receivers

Abstract

An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.

Claims

1. An integrated circuit, comprising:

a first circuit that causes frequency dependent noise, wherein the first circuit is clocked based on a first clock signal;

a second circuit that is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range;

a third circuit that is rate dependent, wherein the third circuit is clocked based on an operation dependent clock signal; and

a clock module that generates the first clock signal having a rate such that frequency dependent noise components associated with the first clock signal are outside the given frequency range and that produces the operation dependent clock signal from the first clock signal.

2. The integrated circuit of claim 1, wherein the clock module further comprises:

a rate adapting module coupled to produce the operation dependent clock signal from the first clock signal.

3. The integrated circuit of claim 2, wherein:

the first circuit includes an analog to digital converter, wherein a digital portion of the analog to digital converter is clocked based on the first clock signal;

the second circuit includes a low noise amplifier; and

the third circuit includes a baseband processing module, wherein the third circuit is clocked based on the operation dependent clock signal.

4. The integrated circuit of claim 2, wherein the rate adapting module comprises at least one of:

a fractional-N frequency synthesizer;

direct digital frequency synthesizer;

a phase locked loop; and

digital logic circuitry.

5. The integrated circuit of claim 2, wherein the rate adapting module functions to:

establish an adjustment factor based on the rate dependency of the third circuit and the first clock signal; and

adjust the rate of the first clock signal based on the adjustment factor to produce the operation dependent clock signal.

6. The integrated circuit of claim 1, wherein the clock module functions to:

for an initial rate of the first clock signal, determine whether the frequency dependent noise components are within the given frequency range; and

when the frequency dependent noise components are within the given frequency range, adjust the rate of the first clock signal by calculation such that the frequency dependent noise components associated with the first clock signal are outside the given frequency range.

7. The integrated circuit of claim 1, wherein the frequency dependent noise comprises at least one of:

harmonic signal components;

spurs; and

digital noise.

8. The integrated circuit of claim 1, wherein the clock module functions to:

determine whether the frequency dependent noise components are within the given frequency range; and

when the frequency dependent noise components are within the given frequency range, incrementally adjust a rate of the first clock signal such that the frequency dependent noise components associated with the first clock signal are outside the given frequency range.

9. A radio frequency integrated circuit (RFIC) comprises:

a low noise amplifier coupled to amplify an inbound radio frequency (RF) signal to produce an amplified RF signal;

a down conversion module coupled to convert the amplified RF signal to a down converted signal based on a local oscillation;

an analog to digital conversion (ADC) module coupled to convert the down converted signal into a digital signal, wherein the ADC conversion module is clocked by a first clock signal;

a baseband processing module coupled to convert the digital signal into inbound data, wherein at least one function of the baseband processing module is clocked by an operation dependent clock signal; and

a clock module coupled to produce the first clock signal and the operation dependent clock signal from the first clock signal, wherein a rate of the first clock signal is set such that frequency dependent noise components associated with the first clock signal are outside a frequency band associated with the inbound RF signal.

10. The RFIC of claim 9,

wherein a rate of the operation dependent clock signal is set based on processing specifications of the digital signal.

11. The RFIC of claim 10, wherein the clock module comprises:

a clock source that generates the first clock signal; and

a rate adjusting module that generates the operation dependent clock signal from the first clock signal.

12. The RFIC of claim 10, wherein the down conversion module comprises:

a local oscillation module coupled to generate the local oscillation based on the operation dependent clock signal;

a mixing module coupled to mix the local oscillation with the amplified RF signal to produce first and second mixed signals; and

a filtering module coupled to filter the first and second mixed signals to produce an inphase component and a quadrature component of the down converted signal.

13. The RFIC of claim 10, wherein the clock module functions to:

establish an adjustment factor based on the rate dependency of the baseband processing module and the first clock signal; and

adjust the rate of the first clock signal based on the adjustment factor to produce the operation dependent clock signal.

14. The RFIC of claim 9, wherein the at least one function of the baseband processing module comprises at least one of:

intermediate frequency to baseband conversion;

fast Fourier transform;

demapping;

deinterleaving;

decoding; and

descrambling.

15. The RFIC of claim 9, wherein the clock module functions to:

for an initial rate of the first clock signal, determine whether the frequency dependent noise components are within the frequency band associated with the inbound RF signal; and

when the frequency dependent noise components are within the frequency band of the inbound RF signal, adjust the rate of the first clock signal by calculation such that the frequency dependent noise components associated with the first clock signal are outside the frequency band associated with the inbound RF signal.

16. The RFIC of claim 9, wherein the clock module functions to:

determine whether the frequency dependent noise components are within the frequency band associated with the inbound RF signal; and

when the frequency dependent noise components are within the frequency band associated with the inbound RF signal, incrementally adjust a rate of the first clock signal such that the frequency dependent noise components associated with the first clock signal are outside the frequency band associated with the inbound RF signal.

17. A method for operating a radio frequency integrated circuit (RFIC), comprising:

clocking a first circuit that causes frequency dependent noise based on a first clock signal;

providing a second circuit that is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range;

clocking a third circuit that is rate dependent based on an operation dependent clock signal;

generating the first clock signal having a rate such that frequency dependent noise components associated with the first clock signal are outside the given frequency range; and

producing the operation dependent clock signal from the first clock signal.

18. The method of claim 17, wherein producing the operation dependent clock signal further comprises:

establishing an adjustment factor based on the rate dependency of the third circuit and the first clock signal; and

adjusting the rate of the first clock signal based on the adjustment factor to produce the operation dependent clock signal.

19. The method of claim 17, wherein generating the first clock signal further comprises:

determining whether the frequency dependent noise components are within the given frequency range; and

when the frequency dependent noise components are within the given frequency range, adjusting the rate of the first clock signal such that the frequency dependent noise components associated with the first clock signal are outside the given frequency range.