ECC bits used as additional register file storage

• US 8,321,761 B1
• Filed: 09/28/2009
• Issued: 11/27/2012
• Est. Priority Date: 09/28/2009
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Gruner, Fred, Qiu, Xiaogang, Tang, Yan Yan
• Primary Examiner(s): Ton, David
• Application Number:
  US12/568,552
• Time in Patent Office: 1,156 Days
• Field of Search: 714/6, 714/769, 714/766, 714/764, 714/763, 714/718
• US Class Current: 714/764
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A memory module includes a plurality of register files. Each register file is associated with a set of error-correcting code (ECC) bits and ECC check/correct logic that can provide error-correcting functionality, if required. When error-correcting functionality is not required, ECC bits are grouped together to form additional register files, thereby providing additional storage space.

Claims

1. A processing unit, comprising:

first and second memory modules;

error-correcting code (ECC) logic coupled to each of the first and second memory modules and configured to correct bit flip errors within the first and second memory modules; and

a memory controller coupled to each of the first and second memory modules and configured to access data within the first and second memory modules, wherein the memory controller is further configured to access data stored in the first memory module while the ECC logic corrects bit flip errors within the second memory module.

2. The processing unit of claim 1, wherein the first and second memory modules are register files.

3. The processing unit of claim 2, wherein the first and second memory modules are random-access memory (RAM) modules.

4. The processing unit of claim 1, wherein the second memory module is coupled to a set of ECC bits and the ECC logic identifies bit flip errors within the second memory module based on the set of ECC bits.

5. The processing unit of claim 4, wherein the ECC logic implements a single error correction/double error detection (SEC/DED) error-correcting code to identify and correct bit flip errors.

6. The processing unit of claim 4, wherein the ECC logic includes an ECC check unit configured to detect bit flip errors and an ECC correct unit configured to correct bit flip errors.

7. A method for correcting bit flip errors within a set of two or more memory modules, comprising:

accessing data stored in a first memory module in the set of two or more memory modules; and

correcting one or more bit flip errors within a second memory module in the set of two or more memory modules independently of the first memory module being accessed.

8. The method of claim 7, wherein the first and second memory modules are register files.

9. The method of claim 8, wherein the first and second memory modules are random-access memory (RAM) modules.

10. The method of claim 7, wherein the step of correcting one or more bit flip errors includes identifying bit flip errors within the second memory module based on a set of ECC bits coupled to the second memory module.

11. The method of claim 10, wherein bit flip errors are identified using a single error correction/double error detection (SEC/DED) error-correcting code.

12. A general-purpose computer system, comprising:

a processing unit;

a memory unit having register files;

a memory controller coupled to the memory unit; and

ECC logic coupled to the memory unit and configured to correct bit flip errors within the memory unit,

wherein the memory controller is configured to access data within the memory unit while the ECC logic corrects the bit flip errors within the memory unit.

13. The computer system of claim 12, wherein the memory unit comprises first and second memory modules.

14. The computer system of claim 13, wherein the memory controller is coupled to each of the first and second memory modules and is configured to access data within the first and second memory modules.

15. The computer system of claim 14, wherein the ECC logic coupled to each of the first and second memory modules.

16. The computer system of claim 15, wherein the memory controller is configured to access data stored in the first memory module while the ECC logic corrects bit flip errors within the second memory module.

17. The computer system of claim 16, wherein the first and second memory modules are random-access memory (RAM) modules.

18. The computer system of claim 16, further comprising a set of ECC bits coupled to the second memory module, wherein the ECC logic identifies bit flip errors within the second memory module based on the set of ECC bits.

19. The computer system of claim 12, wherein the ECC logic implements a single error correction/double error detection (SEC/DED) ECC to identify and correct bit flip errors.