Method and apparatus for providing timing information while designing a multi-cell circuit

• US 8,321,830 B2
• Filed: 12/21/2010
• Issued: 11/27/2012
• Est. Priority Date: 12/21/2010
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hannan, Pete J., Skowronski, Frank P., Schreiber, Jeremy, Krug, Cory P., Snyder, Timothy R.
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US12/974,856
• Publication Number:
  US 20120159415A1
• Time in Patent Office: 707 Days
• Field of Search: 716/139
• US Class Current: 716/139
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method and apparatus are described for providing timing information to a view placement interactive (VPI) tool user designing a multi-cell circuit. A circuit design comprising a plurality of cells is displayed to the user. Each cell includes a pre-characterized circuit structure. A graphical user interface (GUI) may be used to request a cell placement change, a design connectivity change or a cell type change. The circuit design is modified to implement the requested change, an incremental static timing analysis is performed, and the resulting timing information associated with the requested change is presented on the displayed circuit design. Timing information may be displayed directly on a cell that receives an output from the particular cell, and/or may be displayed adjacent to the particular cell. The timing information may include current and previous frequency slack information associated with each input and output pin of the particular cell.

Claims

1. A method of providing timing information to a view placement interactive (VPI) tool user designing a multi-cell circuit, the method comprising:

displaying a circuit design comprising a plurality of cells to the user, each cell including a pre-characterized circuit structure;

receiving a user input associated with a particular one of the cells selected by the user;

determining, based on the user input, whether the user is requesting a cell placement change, a design connectivity change or a cell type change, wherein a netlist change is detected if it is determined that a cell placement or design connectivity change is requested by the user;

modifying the displayed circuit design to implement the change requested by the user; and

presenting timing information associated with the requested change on the displayed circuit design.

2. The method of claim 1 wherein wire parasitics are generated if a netlist change is detected.

3. The method of claim 2 wherein a netlist change is communicated if wire parasitics are generated or a cell type change is requested by the user.

4. The method of claim 3 wherein an incremental static timing procedure is performed in response to receiving the netlist change communication.

5. The method of claim 4 further comprising:

determining updated timing information including a frequency slack value for each input and output pin of the particular cell in response to performing the incremental static timing procedure.

6. The method of claim 1 wherein timing information associated with an output pin of the particular cell is presented directly on a cell that is connected to the output pin.

7. The method of claim 1 wherein timing information is presented adjacent to the particular cell.

8. The method of claim 7 wherein the timing information includes current frequency slack information associated with each input and output pin of the particular cell.

9. The method of claim 8 wherein the timing information includes frequency slack information associated with each input and output pin of the particular cell before a cell placement change, a design connectivity change or a cell type change is performed.

10. A method of providing timing information to a view placement interactive (VPI) tool user designing a multi-cell circuit, the method comprising:

displaying a circuit design comprising a plurality of cells to the user, each cell including a pre-characterized circuit structure having at least one input pin and at least one output pin;

receiving a user input associated with a particular one of the cells selected by the user;

modifying the displayed circuit design in response to receiving the user input; and

presenting timing information on the displayed circuit design, wherein the timing information is presented by performing at least one of;

displaying timing information associated with an output pin of the particular cell directly on a cell that is connected to the output pin of the particular cell, or

displaying timing information associated with each input pin and output pin of the particular cell adjacent to the particular cell.

11. The method of claim 10 wherein the timing information includes frequency slack information.

12. An apparatus for interactively designing a multi-cell circuit, the apparatus comprising:

a display configured to present a circuit design comprising a plurality of cells to a user, each cell including of a pre-characterized circuit structure;

a graphical user interface (GUI) used to generate a user input associated with a particular one of the cells selected by the user;

a view placement interactive (VPI) tool configured to receive the user input and determine, based on the user input, whether the user is requesting a cell placement change, a design connectivity change or a cell type change, wherein a netlist change is detected if it is determined that a cell placement or design connectivity change is requested by the user; and

a timing analysis engine configured to modify the circuit design presented on the display to implement the change requested by the user, and present timing information associated with the requested change on the display.

13. The apparatus of claim 12 wherein the timing information includes a frequency slack value for each input and output pin of the particular cell.

14. The apparatus of claim 12 wherein timing information associated with an output pin of the particular cell is presented directly on a cell that is connected to the output pin.

15. The apparatus of claim 12 wherein the timing information is presented adjacent to the particular cell.

16. The apparatus of claim 15 wherein the timing information includes current frequency slack information associated with each input and output pin of the particular cell.

17. The apparatus of claim 16 wherein the timing information includes frequency slack information associated with each input and output pin of the particular cell before a cell placement change, a design connectivity change or a cell type change is performed.

18. An apparatus for designing a multi-cell circuit, the apparatus comprising:

a display configured to present a circuit design comprising a plurality of cells to a user, each cell including a pre-characterized circuit structure having at least one input pin and at least one output pin;

a view placement interactive (VPI) tool configured to receive a user input associated with a particular one of the cells selected by the user; and

a timing analysis engine configured to receive wire parasitic or cell type change information from the VPI tool, modify the circuit design presented on the display, and present timing information on the display, wherein the timing information is presented by performing at least one of;

displaying timing information associated with an output pin of the particular cell directly on a cell that is connected to the output pin of the particular cell, or

displaying timing information associated with each input pin and output pin of the particular cell adjacent to the particular cell.

19. The apparatus of claim 18 wherein the timing information includes frequency slack information.

20. A circuit design system including a non-transitory computer-readable storage medium containing a set of instructions for interactively providing timing information to a view placement interactive (VPI) tool user designing a multi-cell circuit, the set of instructions comprising:

a first instruction for displaying a circuit design comprising a plurality of cells to the user, each cell including a pre-characterized circuit structure;

a second instruction for determining, based on a user input associated with a particular one of the cells selected by the user, whether the user is requesting a cell placement change, a design connectivity change or a cell type change;

a third instruction for modifying the displayed circuit design to implement the change requested by the user, wherein a netlist change is detected if it is determined that a cell placement or design connectivity change is requested by the user; and

a fourth instruction for presenting timing information associated with the requested change on the displayed circuit design.