Stacked-die electronics package with planar and three-dimensional inductor elements

• US 8,324,023 B2
• Filed: 04/15/2011
• Issued: 12/04/2012
• Est. Priority Date: 07/13/2006
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lam, Ken
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US13/088,296
• Publication Number:
  US 20110193192A1
• Time in Patent Office: 599 Days
• Field of Search: 438/107, 257/E27.01, 257/E21.5, 257/531, 257/686
• US Class Current: 438/107
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Claims

1. A method of forming one or more passive components on a plurality of substrates, the method comprising:

selecting a first substrate and a second substrate such that an area of the second substrate is less than an area of the first substrates;

forming at least one integrated circuit on a front side of each of the first and second substrates;

forming a plurality of bond pads on the front side of the first substrate;

forming a photoresist layer over a back side of the second substrate;

patterning and etching the photoresist layer to form one or more passive component structures on the back side of the second substrate;

filling the etched areas of the patterned and etched photoresist with a metal; and

electrically bonding the one or more passive component structures to selected ones of the plurality of bond pads.

2. The method of claim 1 further comprising:

bonding the back side of the second substrate to the front side of the first substrate;

mounting both the first and second substrates into a semiconductor package;

forming wire bonds from at least one of the two substrates to the semiconductor package; and

forming an encapsulant over the first and second substrates and the plurality of wire bonds.

3. The method of claim 1 further comprising removing substantially all of the remaining etched and patterned photoresist layer.

4. The method of claim 1 further comprising forming a dielectric layer over the back side of the second substrate prior to forming the photoresist layer.

5. The method of claim 1 further comprising forming a protective coating over the at least one integrated circuit of the second substrate prior to forming the photoresist layer over the back side of the second substrate.

6. The method of claim 1 further comprising forming a metal seed layer over the back side of the second substrate prior to forming the photoresist layer.

7. The method of claim 1 further comprising:

forming a dielectric layer over the back side of the second substrate; and

forming a metal seed layer over the dielectric layer prior to forming the photoresist layer.

8. The method of claim 4 further comprising selecting the dielectric layer to be comprised of a high-k dielectric material.

9. A method of forming one or more passive components on a plurality of substrates, the method comprising:

selecting a first substrate and a second substrate such that an area of the second substrate is less than an area of the first substrate;

forming at least one integrated circuit on a front side of each of the first and second substrates;

forming a plurality of bond pads on the front side of the first substrate;

forming a first portion of at least one passive component structure on a back side of the second substrate;

forming a second portion of at least one passive component structure over the at least one integrated circuit on the front side of the first substrate, the second portion being a mirror image of the first portion; and

electrically bonding the first and second portions of the at least on passive component structure.

10. The method of claim 9 further comprising:

forming a photoresist layer over the back side of the second substrate and the front side of the first substrate;

patterning and etching each of the photoresist layers to form the first and second portions of the one or more passive component structures; and

filling the etched areas of the patterned and etched photoresist layers with a metal.

11. The method of claim 9 further comprising:

bonding the back side of the second substrate to the front side of the first substrate;

mounting both the first and second substrates into a semiconductor package;

forming wire bonds from at least one of the two substrates to the semiconductor package; and

forming an encapsulant over the first and second substrates and the plurality of wire bonds.

12. The method of claim 10 further comprising removing substantially all of the remaining etched and patterned photoresist layers.

13. The method of claim 10 further comprising forming a dielectric layer over each of the back side of the second substrate and the front side if the first substrate prior to forming the photoresist layers.

14. The method of claim 10 further comprising forming a protective coating over the at least one integrated circuit of the second substrate prior to forming the photoresist layer over the back side of the second substrate.

15. The method of claim 10 further comprising forming a metal seed layer over each of the back side of the second substrate and the front side of the first substrate prior to forming the photoresist layers.

16. The method of claim 10 further comprising:

forming a dielectric layer over each of the back side of the second substrate and the front side of the first substrate; and

forming a metal seed layer over each of the dielectric layers prior to forming the photoresist layers.

17. The method of claim 13 further comprising selecting the dielectric layers to be comprised of a high-k dielectric material.