Power semiconductor device packaging

• US 8,324,025 B2
• Filed: 04/09/2011
• Issued: 12/04/2012
• Est. Priority Date: 04/22/2010
• Status: Expired due to Fees

• Current Assignee: Team Pacific Corporation
• Original Assignee: Team Pacific Corporation
• Inventors: Saboco, Romeo Alvarez
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/083,531
• Publication Number:
  US 20110260305A1
• Time in Patent Office: 605 Days
• Field of Search: 257/E21.506, 257/E23.052, 257/666, 257669-671, 257/676, 257/678, 257/692, 257/712, 257/727, 257/787, 438/106, 438110-112, 438/121, 438/123, 438/124
• US Class Current: 438/111
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4809 Loop shape
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48096 the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/48747 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48799 Principal constituent of the connecting portion of the wire connector being Copper (Cu)
• CPC Class Codes: H01L 2224/48847 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49112 the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Claims

1. A method for packaging one or more power semiconductor devices, comprising:

constructing a lead frame comprising one or more base die paddles, a plurality of lead terminals, and a tie bar assembly;

connecting said one or more base die paddles of said lead frame to said lead terminals by said tie bar assembly, wherein said tie bar assembly mechanically couples said one or more base die paddles to each other and to said lead terminals;

selectively configuring said tie bar assembly to isolate said lead terminals from said one or more base die paddles; and

creating a plurality of selective connections between one or more of said lead terminals and said one or more power semiconductor devices mounted on said one or more base die paddles;

whereby said selective configuration of said tie bar assembly and said selective connections created between said one or more of said lead terminals and said one or more power semiconductor devices enable flexible packaging of one or more isolated power semiconductor devices and one or more non-isolated power semiconductor devices and increases power handling capacity of said packaged one or more power semiconductor devices.

2. The method of claim 1, wherein said tie bar assembly comprises:

base paddle tie bars that connect said one or more base die paddles of said lead frame to each other;

side tie bars that extend at opposing ends of said lead frame and between adjacent said base die paddles of said lead frame, and connect said one or more base die paddles to said lead terminals; and

terminal tie bars that connect said lead terminals of said lead frame to each other.

3. The method of claim 1, further comprising selectively connecting one or more of said isolated lead terminals to said mounted one or more power semiconductor devices by wire bonding for enabling flexible connections of said isolated lead terminals to said mounted one or more power semiconductor devices.

4. The method of claim 1, wherein said packaging of said one or more isolated power semiconductor devices comprises:

mounting a metallized substrate on one or more of said one or more base die paddles of said lead frame; and

mounting said one or more power semiconductor devices on said mounted metallized substrate.

5. The method of claim 1, wherein said packaging of said one or more non-isolated power semiconductor devices comprises directly mounting said one or more power semiconductor devices on said one or more base die paddles of said lead frame.

6. The method of claim 1, wherein said tie bar assembly is selectively configured to utilize said isolated lead terminals as one of common lead terminals and individual lead terminals.

7. The method of claim 1, wherein said tie bar assembly is selectively configured to utilize two of said lead terminals as a common source and one of said lead terminals as a gate for increasing said power handling capacity of said one or more power semiconductor devices.

8. The method of claim 1, further comprising creating a power module by selectively configuring said tie bar assembly of said lead frame as a common terminal between adjacent said one or more power semiconductor devices.

9. The method of claim 1, wherein said tie bar assembly is selectively configured to flexibly utilize said lead terminals as a drain lead terminal, a gate lead terminal, and a source lead terminal.

10. The method of claim 1, further comprising connecting two of said lead terminals of said lead frame to a source, and one of said lead terminals of said lead frame to a gate, and leaving one of said base die paddles as a drain for increasing said power handling capacity of said mounted one or more power semiconductor devices, wherein said gate, said source, and said drain are three terminals of said mounted one or more power semiconductor devices.

11. The method of claim 1, further comprising configuring one or more of said isolated lead terminals as unused contacts for increasing safety of usage of said mounted one or more power semiconductor devices.

12. A lead frame for packaging one or more power semiconductor devices, comprising:

a plurality of lead terminals;

one or more base die paddles connected to said lead terminals by a tie bar assembly; and

said tie bar assembly selectively configured to isolate said lead terminals from said one or more base die paddles and to enable creation of a plurality of selective connections between one or more of said lead terminals and said one or more power semiconductor devices mounted on said one or more base die paddles, wherein said tie bar assembly mechanically couples said one or more base die paddles to each other and to said lead terminals;

whereby said selectively configured tie bar assembly enables flexible packaging of one or more isolated power semiconductor devices and one or more non-isolated power semiconductor devices and increases power handling capacity of said packaged one or more power semiconductor devices.

13. The lead frame of claim 12, wherein said lead terminals extend to a predetermined elevation from said one or more base die paddles.

14. The lead frame of claim 12, wherein said tie bar assembly comprises:

base paddle tie bars that connect said one or more base die paddles of said lead frame to each other;

side tie bars that extend at opposing ends of said lead frame and between adjacent said base die paddles of said lead frame, and connect said one or more base die paddles to said lead terminals; and

terminal tie bars that connect said lead terminals of said lead frame to each other.

15. The lead frame of claim 12, wherein said isolated lead terminals are utilized as one of common lead terminals and individual lead terminals.

16. The lead frame of claim 12, wherein two of said lead terminals are utilized as a common source and one of said lead terminals is utilized as a gate for increasing said power handling capacity of said one or more power semiconductor devices.

17. The lead frame of claim 12, wherein said lead terminals are flexibly utilized as a drain lead terminal, a gate lead terminal, and a source lead terminal for said mounted one or more power semiconductor devices.

18. The lead frame of claim 12, wherein one or more of said isolated lead terminals are selectively connected to said mounted one or more power semiconductor devices by wire bonding for enabling flexible connections of said isolated lead terminals to said mounted one or more power semiconductor devices.

19. The lead frame of claim 12, wherein two of said lead terminals are connected to a source, one of said lead terminals is connected to a gate, and one of said base die paddles is left as a drain for increasing said power handling capacity of said mounted one or more power semiconductor devices, wherein said gate, said source, and said drain are three terminals of said mounted one or more power semiconductor devices.

20. The lead frame of claim 12, wherein said tie bar assembly is selectively configured as a common terminal between adjacent said one or more power semiconductor devices for creating a power module.

21. A method for packaging one or more power semiconductor devices, comprising:

constructing a lead frame comprising one or more base die paddles, a plurality of lead terminals, and a tie bar assembly;

connecting said one or more base die paddles of said lead frame to said lead terminals by said tie bar assembly, wherein said tie bar assembly mechanically couples said one or more base die paddles to each other and to said lead terminals;

mounting said one or more power semiconductor devices on said one or more base die paddles;

selectively configuring said tie bar assembly to isolate said lead terminals from said one or more base die paddles and to enable creation of a plurality of selective connections between one or more of said lead terminals and said mounted one or more power semiconductor devices; and

selectively connecting one or more of said isolated lead terminals to said mounted one or more power semiconductor devices by wire bonding for enabling flexible connections of said isolated lead terminals to said mounted one or more power semiconductor devices.

22. The method of claim 21, further comprising encapsulating said mounted one or more power semiconductor devices in an encapsulating package body.

23. The method of claim 21, further comprising:

mounting a metallized substrate on one or more of said one or more base die paddles of said lead frame prior to said mounting of said one or more power semiconductor devices; and

mounting said one or more power semiconductor devices on said mounted metallized substrate to create an isolated power semiconductor device package.

24. A semiconductor package comprising:

a lead frame comprising one or more base die paddles, a plurality of lead terminals, and a tie bar assembly, wherein said tie bar assembly mechanically couples said one or more base die paddles to each other and to said lead terminals;

one or more power semiconductor devices mounted on one or more of said one or more base die paddles of said lead frame and/or a metallized substrate mounted on one or more of said one or more base die paddles;

said tie bar assembly selectively configured to isolate said lead terminals from said one or more base die paddles and to enable creation of a plurality of selective connections between one or more of said lead terminals and said mounted one or more power semiconductor devices; and

wire bonds that selectively connect one or more of said isolated lead terminals to said mounted one or more power semiconductor devices.

25. The semiconductor package of claim 24, further comprising an encapsulating package body that encapsulates said mounted one or more power semiconductor devices.