Method of manufacturing a semiconductor device

• US 8,324,032 B2
• Filed: 06/03/2011
• Issued: 12/04/2012
• Est. Priority Date: 08/11/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuma, Hideto, Uehara, Ichiro
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US13/152,492
• Publication Number:
  US 20110294266A1
• Time in Patent Office: 550 Days
• Field of Search: 438151-166, 257/E21.561
• US Class Current: 438/154
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: Y10S 438/949 Energy beam treating radiation resist on semiconductor

Abstract

Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing, the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a conductive film over a first semiconductor and a second semiconductor with an insulating film therebetween;

forming a rectangular shape first resist pattern on the conductive film over the first semiconductor, and forming a second resist pattern on the conductive film over the second semiconductor, wherein a thickness of an edge portion of the resist pattern is smaller than thickness of a middle portion of the resist pattern;

forming a rectangular shape first gate electrode over the first semiconductor by a first dry etching using the first resist pattern, and forming a second gate electrode by the first dry etching using the second resist pattern over the second semiconductor, wherein a thickness of an edge portion of the second gate electrode is smaller than a thickness of a middle portion of the second gate electrode;

introducing an impurity element into the first semiconductor with the first gate electrode as a mask to form a first impurity region in the first semiconductor, wherein the first impurity region is not overlapped with the first gate electrode, and introducing an impurity element into the second semiconductor with the second gate electrode as a mask to form a second and a third impurity regions in the second semiconductor, wherein the second impurity region is not overlapped with the second gate electrode and the third impurity region is overlapped with the edge portion of the second gate electrode; and

making the edge portion of the second gate electrode recede by a second dry etching.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the edge portion of the resist pattern has tapered configuration.

3. The method of manufacturing a semiconductor device according to claim 1, wherein a diffraction grating pattern having a plurality of slit portions, or a translucent film portion, is used for forming the resist pattern.

4. The method of manufacturing a semiconductor device according to claim 1, wherein each of the first semiconductor and the second semiconductor is a semiconductor layer formed on an insulating surface.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the first and the second semiconductors are formed in a semiconductor substrate.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is incorporated into an electronic device selected from the group consisting of a video camera, a digital camera, a projector, a head mounted display, a car navigation system, a car stereo, a personal computer, a portable information terminal.

7. A method of manufacturing a semiconductor device comprising the steps of:

forming a conductive film over a first semiconductor and a second semiconductor with an insulating film therebetween;

forming a first resist pattern on the conductive film over the first semiconductor and a second resist pattern on the conductive film over the second semiconductor, wherein a thickness of an edge portion of the first resist pattern and a second thickness of an edge portion of the second resist pattern are smaller than thickness of a middle portion each of the first and the second resist patterns;

forming a first gate electrode by a first dry etching using the first resist pattern, wherein a first thickness of an edge portion of the first gate electrode is smaller than a thickness of a middle portion of the first gate electrode, and forming a second gate electrode by the first dry etching using the second resist pattern, wherein a second thickness of an edge portion of the second gate electrode is smaller than a thickness of a middle portion of the second gate electrode;

removing the first and the second resist patterns;

introducing an impurity element into the first semiconductor with the first gate electrode as a mask to form a first impurity region and a second impurity region in the first semiconductor, wherein the first impurity region is not overlapped with the first gate electrode and the second impurity region is overlapped with the edge portion of the first gate electrode, and introducing the impurity element into the second semiconductor with the second gate electrode as a mask to form a third impurity region and a fourth impurity region in the second semiconductor, wherein the third impurity region is not overlapped with the second gate electrode and the second impurity region is overlapped with the edge portion of the second gate electrode;

making the edge portions of the first and the second gate electrodes recede by a second dry etching;

forming a third resist pattern over the first gate electrode, wherein the second gate electrode is exposed from the third resist pattern; and

making the edge portion of the second gate electrode recede by a third dry etching.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the first and the second thicknesses are the same.

9. The method of manufacturing a semiconductor device according to claim 7, wherein the edge portion of the resist pattern has tapered configuration.

10. The method of manufacturing a semiconductor device according to claim 7, wherein a diffraction grating pattern having a plurality of slit portions, or a translucent film portion, is used for forming the resist pattern.

11. The method of manufacturing a semiconductor device according to claim 7, wherein each of the first semiconductor and the second semiconductor is a semiconductor layer formed on an insulating surface.

12. The method of manufacturing a semiconductor device according to claim 7, wherein the first and the second semiconductors are formed in a semiconductor substrate.

13. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is incorporated into an electronic device selected from the group consisting of a video camera, a digital camera, a projector, a head mounted display, a car navigation system, a car stereo, a personal computer, a portable information terminal.

14. A method of manufacturing a semiconductor device comprising the steps of:

forming a conductive film over a semiconductor with an insulating film therebetween;

forming a rectangular shape first resist pattern on the conductive film, and forming a second resist pattern on the conductive film, wherein a thickness of an edge portion of the second resist pattern is smaller than thickness of a middle portion of the second resist pattern;

forming a rectangular shape first gate electrode by a first dry etching using the first resist pattern, and forming a second gate electrode by the first dry etching using the second resist pattern, wherein a thickness of an edge portion of the second gate electrode is smaller than a thickness of a middle portion of the second gate electrode;

removing the first and the second resist patterns;

introducing an impurity element into the semiconductor with the first gate electrode as a mask to form a first impurity region in the semiconductor, wherein the first impurity region is not overlapped with the first gate electrode, and introducing the impurity element into the semiconductor with the second gate electrode as a mask to form a second and a third impurity regions in the semiconductor, wherein the second impurity region is not overlapped with the second gate electrode and the third impurity region is overlapped with the edge portion of the second gate electrode; and

making the edge portion of the second gate electrode recede by a second dry etching.

15. The method of manufacturing a semiconductor device according to claim 14, wherein the edge portion of the resist pattern has tapered configuration.

16. The method of manufacturing a semiconductor device according to claim 14, wherein a diffraction grating pattern having a plurality of slit portions, or a translucent film portion, is used for forming the resist pattern.

17. The method of manufacturing a semiconductor device according to claim 14, wherein each of the first semiconductor and the second semiconductor is a semiconductor layer formed on an insulating surface.

18. The method of manufacturing a semiconductor device according to claim 14, wherein the first and the second semiconductors are formed in a semiconductor substrate.

19. The method of manufacturing a semiconductor device according to claim 14, wherein the semiconductor device is incorporated into an electronic device selected from the group consisting of a video camera, a digital camera, a projector, a head mounted display, a car navigation system, a car stereo, a personal computer, a portable information terminal.