Method and structure of an integrated CMOS and MEMS device using air dielectric

• US 8,324,047 B1
• Filed: 11/13/2010
• Issued: 12/04/2012
• Est. Priority Date: 11/13/2009
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yang, Xiao “Charles”
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US12/945,846
• Time in Patent Office: 752 Days
• Field of Search: None
• US Class Current: 438/240
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence

Abstract

In a specific embodiment, the present invention provides an integrated circuit device. The device includes a base substrate having a surface region and an interlayer dielectric material overlying the surface region. The device also has a thickness of single crystal silicon material overlying the interlayer dielectric material. In one or more embodiments, the thickness of single crystal silicon material has a front region and a backside region. The front region faces the interlayer dielectric material. In a preferred embodiment, the device has a plurality of transistor devices spatially arranged in the thickness of silicon crystal silicon material. Each of the transistor devices has a gate structure within a region of the interlayer dielectric material. The device also has an enclosure housing configured to form a cavity between the backside region of the thickness of silicon material and an upper inside region of the enclosure housing.

Claims

1. An integrated circuit device comprising:

a base substrate having a surface region;

an interlayer dielectric material overlying the surface region;

a thickness of single crystal silicon material overlying the interlayer dielectric material, the thickness of single crystal silicon material having a font region and a backside region, the front region facing the interlayer dielectric material;

a plurality of transistor devices spatially arranged in the thickness of silicon crystal silicon material, each of the transistor devices having a gate structure within a region of the interlayer dielectric material; and

an enclosure housing configured to form a cavity between the backside region of the thickness of silicon material and an upper inside region of the enclosure housing.

2. The device of claim 1 wherein the base substrate is made of a semiconductor material, a conductor material, or an insulating material.

3. The device of claim 1 wherein the thickness of single crystal silicon material is 100 micrometers or less.

4. The device of claim 1 wherein the backside of the silicon crystal silicon material is thinned.

5. The device of claim 1 wherein the interlayer dielectric material comprises two or more materials.

6. The device of claim 1 wherein each of the transistor devices is located within a well region formed within a portion of the thickness of single crystal silicon material.

7. The device of claim 1 wherein each of the transistor device comprises an MOS device.

8. The device of claim 1 wherein the enclosure housing is made of a semiconductor, a conductor, or a dielectric.

9. The device of claim 1 further comprising an inert gas within the cavity.

10. The device of claim 1 further comprising a dielectric material within the cavity.

11. The device of claim 1 wherein the cavity is characterized by a dielectric constant of about 1 or slightly greater.

12. A method for fabricating an integrated circuit device, the method comprising:

providing a bulk substrate;

forming a dielectric material overlying the bulk substrate;

forming a thickness of single crystal silicon material overlying the dielectric material, the thickness of single crystal silicon material having a front region and a backside region;

forming an interlayer dielectric material overlying the thickness of single crystal silicon material;

forming a plurality of transistor devices spatially arranged in the thickness of silicon crystal silicon material, each of the transistor devices having a gate structure within a region of the interlayer dielectric material;

bonding the interlayer dielectric material to a base substrate, the base substrate having a surface region, the interlayer dielectric material being bonded to the surface region;

removing the bulk substrate;

removing the dielectric material; and

forming an enclosure housing configured to form a cavity between the backside region of the thickness of silicon material and an upper inside region of the enclosure housing.

13. The method of claim 12 wherein the base substrate is made of a semiconductor material, a conductor material, or an insulating material.

14. The method of claim 12 wherein the thickness of single crystal silicon material is 100 micrometers and less.

15. The method of claim 12 wherein the backside of the silicon crystal silicon material is thinned.

16. The device of claim 12 wherein the interlayer dielectric material comprises two or more materials.

17. The device of claim 12 wherein each of the transistor devices is provided within a well region formed within a portion of the thickness of single crystal silicon material.

18. The device of claim 12 wherein each of the transistor devices comprises an MOS device.

19. The device of claim 12 wherein the enclosure housing is made of a semiconductor, a conductor, or a dielectric.

20. The device of claim 12 wherein the cavity comprises an inert gas.