Semiconductor device and manufacturing method thereof

• US 8,324,094 B2
• Filed: 07/20/2011
• Issued: 12/04/2012
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Endo, Masato, Kato, Tatsuya
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US13/186,712
• Publication Number:
  US 20110275213A1
• Time in Patent Office: 503 Days
• Field of Search: 430/311, 430/312, 430/313, 430/314, 430/315, 430/316, 430/317, 430/322, 430/323, 430/324, 438/618, 438/620, 438/622, 438/637, 438/638, 438/639, 438/671, 438/696, 438/700, 438/702, 438/703, 438/FOR.100, 438/FOR.118, 257/E21.023, 257/E21.035, 257/E21.036, 257/E21.037, 257/E23.038, 257/E21.039, 257/E21.232, 257/E21.233, 257/E21.235
• US Class Current: 438/638
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout

Abstract

A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.

Claims

1. A semiconductor device manufacturing method comprising:

forming, on an insulating layer, a plurality of first mask layers and a second mask layer which is arranged between the first mask layers and has a width larger than that of a first mask layer, the first mask layers and the second mask layer being arrayed at equal spaces;

reducing a width of each of the first mask layers and the second mask layer by selectively etching the first mask layers and the second mask layer;

forming a plurality of sidewalls on side surfaces of the first mask layers and the second mask layer;

removing the first mask layers and the second mask layer to leave the sidewalls;

selectively etching the insulating layer using the sidewalls as a mask to form, in the insulating layer, a plurality of first trenches and a second trench which is arranged between the first trenches and has a width larger than that of a first trench; and

burying a conductor in the first trenches and the second trench to form, in the insulating layer, a plurality of first interconnection layers and a second interconnection layer having a width larger than that of a first interconnection layer.

2. The method according to claim 1, wherein

each of the width and space of the first mask layers is a minimum feature size ascribable to an exposure technique, and

a width of each of the sidewalls is smaller than the minimum feature size.

3. The method according to claim 2, wherein in the step of reducing the width of each of the first mask layers and the second mask layer, letting “

2F”

be the minimum feature size, the width of the first mask layer is reduced from “

2F”

to “

F”

.

4. The method according to claim 2, wherein letting “

2F”

be the minimum feature size, the width of the second mask layer satisfies

2F×

n (n is a natural number of not less than

     1).

5. The method according to claim 2, wherein

the width of the first interconnection layer is half of the minimum feature size, and

the space between the first interconnection layers is half of the minimum feature size.

6. The method according to claim 1, wherein letting “

F”

be the width of the first interconnection layer, the width of the second interconnection layer satisfies

2F×

n−

F (n is a natural number of not less than

     1).

7. The method according to claim 1, wherein the first mask layers and the second mask layer are made of one of silicon nitride and amorphous silicon.

8. The method according to claim 1, wherein a space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.

9. The method according to claim 1, wherein the first interconnection layers include shallow interconnections and deep interconnections which are alternately arranged.

10. The method according to claim 1, wherein the first interconnection layers and the second interconnection layer are made of one material selected from the group consisting of copper (Cu), aluminum (Al), and ruthenium (Ru).

11. The method according to claim 1, wherein the sidewalls are made of a material having an etching selectivity with respect to the first mask layers and the second mask layer.