Chip-stacked image sensor having image signal sensing cell, where the image signal sensing cell has photodiodes and charge transmission transistors commonly connected to charge transmission pads

• US 8,324,553 B2
• Filed: 03/21/2008
• Issued: 12/04/2012
• Est. Priority Date: 03/26/2007
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Siliconfile Technologies Incorporated (SK Hynix Inc.)
• Inventors: Lee, Do-Young
• Primary Examiner(s): Le, Que T
• Assistant Examiner(s): BENNETT, JENNIFER D
• Application Number:
  US12/529,499
• Publication Number:
  US 20100019130A1
• Time in Patent Office: 1,719 Days
• Field of Search: 348/272, 348/274, 348/275, 348/281, 348/294, 348/302, 348/303, 348/304, 348/308, 257/257, 257/258, 257/291, 257/431, 257/440, 257/443, 257/444, 257/448, 257/459, 250/208.1, 250/239, 250/214.1, 250/214.R, 250/226
• US Class Current: 250/214.R
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

A chip-stacked image sensor obtained by embodying an image sensor cell in two chips and combining the chips with each other is provided. The chip-stacked image sensor includes first and second semiconductor chips. The first semiconductor chip includes a plurality of image signal sensing cells for generating image charges corresponding to image signals sensed by at least four photodiodes and outputting the generated image charges through at least two common terminals and a plurality of image charge transmission pads. The second semiconductor chip includes a plurality of image signal conversion cells for converting the image signals into electrical signals and a plurality of image charge receiving pads. Here, the image charges generated by the image signal sensing cells are transmitted to corresponding image signal conversion cells via the plurality of image charge transmission pads and the plurality of image charge receiving pads.

Claims

1. A chip-stacked image sensor comprising:

a first semiconductor chip comprising a plurality of image signal sensing cells for generating image charges corresponding to image signals, wherein each of the image signal sensing cells comprises at least four photodiodes and at least two image charge transmission pads; and

a second semiconductor chip comprising a plurality of image signal conversion cells for converting the image signals into electrical signals, wherein each of the image signal conversion cells comprises at least two image charge receiving pads,

wherein the image charges generated by a first image signal sensing cell in the plurality of image signal sensing cells are transmitted to a first image signal conversion cell in the plurality of image signal conversion cells via the at least two image charge transmission pads of the first image signal sensing cell and the at least two image charge receiving pads of the first image signal conversion cell, and

wherein the first image signal sensing cell comprises;

a first photodiode (0,0);

a second photodiode (1,1) disposed in a diagonal direction of the first photodiode (0,0);

a third photodiode (1,0) disposed in a side of the second photodiode (1,1) and over the first photodiode (0, 0);

a fourth photodiode (2,1) disposed over the second photodiode (1, 1);

a first charge transmission transistor M1 comprising a terminal connected to the first photodiode (0,0) and a gate applied with a first charge transmission signal Tx0;

a second charge transmission transistor M2 comprising a terminal connected to the second photodiode (1,1 and a gate applied with a second charge transmission signal Tx1;

a third charge transmission transistor M6 comprising a terminal connected to the third photodiode (1,0) and a gate applied with the second charge transmission signal Tx1;

a fourth charge transmission transistor M7 comprising a terminal connected to the fourth photodiode (2,1) and a gate applied with a third charge transmission signal Tx2;

a first image charge transmission pad P1-1 commonly connected to the other terminal of the first charge transmission transistor M1 and the other terminal of the second charge transmission transistor M2; and

a second image charge transmission pad P1-2 commonly connected to the other terminal of the third charge transmission transistor M6 and the other terminal of the fourth charge transmission transistor M7.

2. The chip-stacked image sensor of claim 1,

wherein the image charge transmission pads of the first semiconductor chip and the image charge receiving pads of the second semiconductor chip are arranged in one-to-one correspondence, and

wherein the first and second semiconductor chips are combined with each other.

3. The chip-stacked image sensor of claim 1, wherein the first image signal conversion cell comprises:

a first image charge receiving pad P2-1;

a second image charge receiving pad P2-2;

a first common reset transistor M3 comprising a terminal connected to a selection signal Sx, the other terminal connected to the first image charge receiving pad P2-1, and a gate applied with a first reset signal Rx01;

a first common conversion transistor M4 comprising a terminal connected to the selection signal Sx, the other terminal for outputting a first conversion voltage OUT1, and a gate connected to the first image charge receiving pad P2-1;

a second common reset transistor M8 comprising a terminal connected to the selection signal Sx, the other terminal connected to the second image charge receiving pad P2-2, and a gate applied with a second reset signal Rx12; and

a second common conversion transistor M9 comprising a terminal connected to the selection signal Sx, the other terminal for outputting a second conversion voltage OUT2, and a gate connected to the second image charge receiving pad P2-2.

4. The chip-stacked image sensor of claim 3, wherein when the first and second semiconductor chips are combined with each other, a position of the first image charge transmission pad P1-1 is matched with a position of the first image charge receiving pad P2-1, and a position of the second image charge transmission pad P1-2 is matched with a position of the second image charge receiving pad P2-2.

5. The chip-stacked image sensor of claim 1, wherein the first image signal conversion cell comprises:

a first image charge receiving pad P2-1;

a second image charge receiving pad P2-2;

a first common reset transistor M3 comprising a terminal connected to a selection signal Sx, the other terminal connected to the first image charge receiving pad P2-1, and a gate applied with a first reset signal Rx01;

a first common conversion transistor M4 comprising a terminal connected to a voltage source Vdd, the other terminal for outputting a first conversion voltage OUT1, and a gate connected to the first image charge receiving pad P2-1;

a second common conversion transistor M9 comprising a terminal connected to the voltage source Vdd, the other terminal for outputting a second conversion voltage OUT2, and a gate connected to the second image charge receiving pad P2-2; and

a second common reset transistor M8 comprising a terminal connected to the selection signal Sx, the other terminal connected to the second image charge receiving pad P2-2, and a gate applied with a second reset signal Rx12.

6. The chip-stacked image sensor of claim 1, wherein the first image signal conversion cell comprises:

a first image charge receiving pad P2-1;

a second image charge receiving pad P2-2;

a first common reset transistor M3 comprising a terminal connected to a voltage source Vdd, the other terminal connected to the first image charge receiving pad P2-1, and a gate applied with a first reset signal Rx01;

a first common conversion transistor M4 comprising a terminal connected to the voltage source Vdd and a gate connected to the first image charge receiving pad P2-1;

a first common selection transistor M5 comprising a terminal connected to the other terminal of the first common conversion transistor M4, the other terminal for outputting a first conversion voltage, and a gate applied with a first selection signal Sx01;

a second common reset transistor M8 comprising a terminal connected to the voltage source Vdd, the other terminal connected to the second image charge receiving pad P2-2, and a gate applied with a second reset signal Rx12;

a second common conversion transistor M9 comprising a terminal connected to the voltage source Vdd and a gate connected to the second image charge receiving pad P2-2; and

a second common selection transistor M10 comprising a terminal connected to the other terminal of the second common conversion transistor M9, the other terminal for outputting a second conversion voltage, and a gate applied with a second selection signal Sx12.

7. The chip-stacked image sensor of claim 1,

wherein when the third and fourth photodiodes (1,0) and (2,1) operate in response to the image signals incident via a first filter, the first and second photodiodes (0,0) and (1,1) operate in response to the image signals respectively incident via second and third filters.

8. The chip-stacked image sensor of claim 7, wherein the first filter is a green filter, and each the second and third filters is a red or blue filter.

9. A chip-stacked image sensor comprising:

a first semiconductor chip comprising a plurality of image signal sensing cells for generating image charges corresponding to image signals, wherein each of the image signal sensing cells comprises at least four photodiodes and at least two image charge transmission pads; and

a second semiconductor chip comprising a plurality of image signal conversion cells for converting the image signals into electrical signals, wherein each of the image signal conversion cells comprises at least two image charge receiving pads,

wherein the image charges generated by a first image signal sensing cell in the plurality of image signal sensing cells are transmitted to a first image signal conversion cell in the plurality of image signal conversion cells via the at least two image charge transmission pads of the first image signal sensing cell and the at least two image charge receiving pads of the first image signal conversion cell, and

wherein the first image signal sensing cell comprises;

a first photodiode (0,0);

a second photodiode (1,1) disposed in a diagonal direction of the first photodiode (0, 0);

a third photodiode (1,2) disposed in a side of the second photodiode (1, 1);

a fourth photodiode (2,1) disposed over the second photodiode (1, 1);

a first charge transmission transistor M1 comprising a terminal connected to the first photodiode (0,0) and a gate applied with a first charge transmission signal Tx0;

a second charge transmission transistor M2 comprising a terminal connected to the second photodiode (1,1) and a gate applied with a second charge transmission signal Tx1;

a third charge transmission transistor M6 comprising a terminal connected to the third photodiode (1,2) and a gate applied with the second charge transmission signal Tx1;

a fourth charge transmission transistor M7 comprising a terminal connected to the fourth photodiode (2,1) and a gate applied with a third charge transmission signal Tx2;

a first image charge transmission pad P1-1 commonly connected to the other terminal of the first charge transmission transistor M1 and the other terminal of the second charge transmission transistor M2; and

a second image charge transmission pad P1-2 commonly connected to the other terminal of the third charge transmission transistor M6 and the other terminal of the fourth charge transmission transistor M7.

10. The chip-stacked image sensor of claim 9, wherein the first image signal conversion cell comprises:

a first image charge receiving pad P2-1;

a second image charge receiving pad P2-2;

a first common reset transistor M3 comprising a terminal connected to a selection signal Sx, the other terminal connected to the first image charge receiving pad P2-1, and a gate applied with a first reset signal Rx01;

a first common conversion transistor M4 comprising a terminal connected to the selection signal Sx, the other terminal for outputting a first conversion voltage, and a gate connected to the first image charge receiving pad P2-1;

a second common reset transistor M8 comprising a terminal connected to the selection signal Sx, the other terminal connected to the second image charge receiving pad P2-2, and a gate applied with a second reset signal Rx12; and

a second common conversion transistor M9 comprising a terminal connected to the selection signal Sx, the other terminal for outputting a second conversion voltage, and a gate connected to the second image charge receiving pad P2-2.

11. The chip-stacked image sensor of claim 9, wherein the first image signal conversion cell comprises:

a first image charge receiving pad P2-1;

a second image charge receiving pad P2-2;

a first common reset transistor M3 comprising a terminal connected to a selection signal Sx, the other terminal connected to the first image charge receiving pad P2-1, and a gate applied with a first reset signal Rx01;

a first common conversion transistor M4 comprising a terminal connected to a voltage source Vdd, the other terminal for outputting a first conversion voltage OUT1, and a gate connected to the first image charge receiving pad P2-1;

a second common conversion transistor includes M9 comprising a terminal connected to the voltage source Vdd, the other terminal for outputting a second conversion voltage OUT2, and a gate connected to the second image charge receiving pad P2-2; and

a second common reset transistor M8 comprising a terminal connected to the selection signal Sx, the other terminal connected to the second image charge receiving pad P2-2, and a gate applied with a second reset signal Rx12.

12. The chip-stacked image sensor of claim 9, wherein the first image signal conversion cell comprises:

a first image charge receiving pad P2-1;

a second image charge receiving pad P2-2;

a first common reset transistor M3 comprising a terminal connected to a voltage source Vdd, the other terminal connected to the first image charge receiving pad P2-1, and a gate applied with a first reset signal Rx01;

a first common conversion transistor M4 comprising a terminal connected to the voltage source Vdd and a gate connected to the first image charge receiving pad P2-1;

a first common selection transistor M5 comprising a terminal connected to the other terminal of the first common conversion transistor M4, the other terminal for outputting a first conversion voltage OUT1, and a gate applied with a first selection signal Sx01;

a second common reset transistor M8 comprising a terminal connected to the voltage source Vdd, the other terminal connected to the second image charge receiving pad P2-2, and a gate applied with a second reset signal Rx12;

a second common conversion transistor M9 comprising a terminal connected to the voltage source Vdd and a gate connected to the second image charge receiving pad P2-2; and

a second common selection transistor M10 including comprising a terminal connected to the other terminal of the second common conversion transistor M9, the other terminal for outputting a second conversion voltage, and a gate applied with a second selection signal Sx12.

13. The chip-stacked image sensor of claim 9

wherein when the third and fourth photodiodes (1,2) and (2,1) operate in response to the image signals incident via a first filter, the first and second photodiodes (0,0) and (1,1) operate in response to the image signals respectively incident via second and third filters.

14. The chip-stacked image sensor of claim 13, wherein the first filter is a green filter, and each the second and third filters is a red or blue filter.