Dielectric mesh isolated phase change structure for phase change memory

• US 8,324,605 B2
• Filed: 10/02/2008
• Issued: 12/04/2012
• Est. Priority Date: 10/02/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), Macronix International Co., Ltd.
• Original Assignee: International Business Machines Corporation, Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan, Shih, Yen-Hao, Lee, Ming-Hsiu, Breitwisch, Matthew J., Lam, Chung Hon, Baumann, Frieder H., Flaitz, Philip, Raoux, Simone, Chen, Chieh-Fang
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US12/286,874
• Publication Number:
  US 20100084624A1
• Time in Patent Office: 1,524 Days
• Field of Search: 257/2, 257/E47.001, 257/E21.068, 365/148
• US Class Current: 257/2
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/041 Modification of switching materials after formation, e.g. doping shaping H10N70/061
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/828 Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Claims

1. A method for manufacturing a memory device, the method comprising:

forming a first electrode and a second electrode;

forming a body of phase change memory material between the first and second electrodes, the phase change memory material comprising a chalcogenide material doped with a dielectric material; and

creating a first, active region and a second region within the body of phase change memory material, the creating step comprising;

forming within the first region a first concentration of the phase change material and a second concentration of the dielectric material; and

forming within the first, active region;

a plurality phase change material domains having a first concentration of the phase change material; and

a mesh of the dielectric material at least partially separating the plurality of phase change material domains; and

forming the phase change memory material within the second region in a polycrystalline state with grains without a mesh of the dielectric material surrounding the grains.

2. The method of claim 1, including

forming the body of phase change memory material in a polycrystalline state;

and

the first, active region forming step comprising melting and solidifying the phase change memory material at least once within the first, active region in the body of phase change material without disturbing the polycrystalline state in the second region, thereby forming the plurality of phase change material domains and the mesh of the dielectric material.

3. The method of claim 2, including forming circuitry on the memory device to apply set and reset pulses across the first and second electrodes for writing data, and performing said melting and solidifying by applying a reset pulse across the first and second electrodes.

4. The method of claim 2, including forming circuitry on the memory device to apply set and reset pulses across the first and second electrodes for writing data, and performing said melting and solidifying by applying a set pulse and a reset pulse across the first and second electrodes.

5. The method of claim 1, wherein the chalcogenide material used in the phase change memory material, when not doped with the dielectric material is characterized by a first solid crystalline phase having first volume and by a second solid crystalline phase having second volume, the phase change memory material having a volume in the amorphous phase which is closer to the second volume than the first volume, and wherein the chalcogenide material doped with a dielectric material has a concentration of the dielectric material sufficient to promote formation of the second solid crystalline phase.

6. The method of claim 5, wherein the first solid crystalline phase is a HCP phase, and the second solid crystalline phase is a FCC phase.

7. The method of claim 1, wherein the chalcogenide material used in the phase change memory material, when not doped with the dielectric, is characterized by a plurality of solid crystalline states, and wherein the chalcogenide material doped with a dielectric material has a concentration of the dielectric material sufficient to prevent formation of at least one of the solid crystalline states in the active region.

8. The method of claim 1, wherein the chalcogenide material used in the phase change memory material, when not doped with the dielectric, is characterized by a plurality of solid crystalline states, and wherein the chalcogenide material doped with a dielectric material has a concentration of the dielectric material sufficient to prevent formation of at least one of the solid crystalline states in the first region.

9. The method of claim 1, wherein the dielectric material in the chalcogenide doped with dielectric material is silicon oxide, having a concentration in a range of 10 to 20 at %.

10. The method of claim 1, wherein the chalcogenide material used in the phase change memory material comprises Ge_xSb_yTe_z.

11. The method of claim 1, wherein the chalcogenide material used in the phase change memory material comprises Ge_xSb_yTe_z, where x=2, y=2 and z=5;

and wherein the dielectric material in the chalcogenide doped with dielectric material is silicon oxide, having a concentration in a range of 10 to 20 at %.

12. A phase change memory device, comprising:

a first electrode and a second electrode;

a body of phase change memory material between the first and second electrodes, the phase change memory material comprising a chalcogenide material doped with a dielectric material; and

the body of phase change material having a first, active region and a second region;

the first, active region comprising;

a plurality of phase change material domains having a first concentration of phase change material; and

a mesh of the dielectric material at least partially separating the plurality of phase change material domains; and

the second region being in a polycrystalline state with grains without a mesh of the dielectric material surrounding the grains, the second regain having a second concentration of phase change material, the second concentration being less than the first concentration.

13. The device of claim 12, wherein the chalcogenide material used in the phase change memory material, when not doped with the dielectric is characterized by a first solid crystalline phase having first volume and by a second solid crystalline phase having second volume, the phase change memory material having a volume in the amorphous phase which is closer to the second volume than the first volume, and wherein the chalcogenide material doped with a dielectric material has a concentration of the dielectric material sufficient to promote formation of the second solid crystalline phase.

14. The device of claim 12, wherein the first solid crystalline phase is a HCP phase, and the second solid crystalline phase is a FCC phase.

15. The device of claim 12, wherein the chalcogenide material used in the phase change memory material, when not doped with the dielectric material, is characterized by a plurality of solid crystalline states, and wherein the chalcogenide material doped with a dielectric material has a concentration of the dielectric material sufficient to prevent formation of at least one of the solid crystalline states in the active region.

16. The device of claim 12, wherein the chalcogenide material used in the phase change memory material, when not doped with the dielectric material, is characterized by a plurality of solid crystalline states, and wherein the chalcogenide material doped with a dielectric material has a concentration of the dielectric material sufficient to prevent formation of at least one of the solid crystalline states outside the active region.

17. The device of claim 12, the dielectric material in the chalcogenide doped with a dielectric material is silicon oxide, having a concentration in a range of 10 to 20 at %.

18. The device of claim 12, including circuitry on the memory device to apply set and reset pulses across the first and second electrodes for writing data, and for melting and solidifying the active region by applying at least one reset pulse across the first and second electrodes.

19. The device of claim 12, including circuitry on the memory device to apply set and reset pulses across the first and second electrodes for writing data, and for melting and solidifying the active region by applying at least one set pulse and at least one reset pulse across the first and second electrodes.

20. The device of claim 12, wherein the chalcogenide material used in the phase change memory material comprises Ge_xSb_yTe_z.

21. The device of claim 12, wherein the chalcogenide material used in the phase change memory material comprises Ge_xSb_yTe_z, where x=2, y=2 and z=5;

and wherein the dielectric material is silicon oxide having a concentration in a range of 10 to 20 at %.