Channel layer for a thin film transistor, thin film transistor including the same, and methods of manufacturing the same

• US 8,324,628 B2
• Filed: 02/29/2008
• Issued: 12/04/2012
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Song, I-hun, Park, Young-soo, Kang, Dong-hun, Kim, Chang-jung, Park, Jae-chul
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US12/073,102
• Publication Number:
  US 20090001432A1
• Time in Patent Office: 1,740 Days
• Field of Search: 257/59, 257/60, 257/72, 257/E27.113, 257/E27.116, 438/149, 438/217, 438/478, 438/479
• US Class Current: 257/72
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.

Claims

1. A channel layer for a thin film transistor comprising IZO (indium zinc oxide) doped with a transition metal, wherein the transition metal is at least one selected from the group consisting of Co, Rh, Ir, Mt, Ni, Pd, Pt, Ds, Ag, Au, and Rg, and the channel layer has an electrical conductivity lower than that of an undoped IZO due to the transition metal.

2. The channel layer of claim 1, wherein the channel layer is made of a material expressed with an equation of a(In₂O₃).b(ZnO), where a and b are real numbers such that a>

about 0 and b>

about 0.

3. The channel layer of claim 2, wherein a and b are real numbers such that about 0<

a≦

about 1 and b≧

about 1.

4. The channel layer of claim 1, wherein the transition metal is Ni.

5. The channel layer of claim 1, wherein the doping concentration of the transition metal is about 10³˜

about 10²² atom/cm³.

6. A thin film transistor comprising:

a gate electrode and the channel layer according to claim 1 on a substrate;

a gate insulating layer between the gate electrode and the channel layer; and

a source electrode and a drain electrode which contact ends of the channel layer.

7. The thin film transistor of claim 6, wherein the gate electrode is above the channel layer.

8. The thin film transistor of claim 7, further comprising:

a passivation layer on the gate insulating layer and the gate electrode.

9. The thin film transistor of claim 6, wherein the gate electrode is below the channel layer.

10. The thin film transistor of claim 9, further comprising:

a passivation layer on the gate insulating layer, the channel layer, the source electrode and the drain electrode.

11. A method of forming a channel layer used in a thin film transistor comprising:

providing a semiconductor material layer for forming a channel; and

patterning the semiconductor material layer to form a channel layer,

wherein the semiconductor material layer is an IZO layer doped with a transition metal, the transition metal being at least one selected from the group consisting of Co, Rh, Ir, Mt, Ni, Pd, Pt, Ds, Ag, Au, and Rg, and the channel layer has an electrical conductivity lower than that of an undoped IZO due to the transition metal.

12. The method of claim 11, wherein the channel layer is formed of a material expressed with an equation of a(In₂O₃).b(ZnO), where a and b are real numbers such that a>

about 0 and b>

about 0.

13. The method of claim 12, wherein a and b are real numbers such that about 0<

a ≦

about 1 and b≧

about 1.

14. The method of claim 11, wherein the transition metal is Ni.

15. The method of claim 11, wherein the doping concentration of the transition metal is about 10³˜

about 10²² atom/cm³.

16. A method of manufacturing a thin film transistor comprising:

forming the channel layer according to claim 11 on a substrate;

forming a source electrode and a drain electrode on the channel layer, wherein the source electrode and drain electrode contact ends of the channel layer;

forming a gate insulating layer on exposed portions of the channel layer and the source and drain electrode; and

forming a gate electrode on the gate insulating layer.

17. The method of claim 16, further comprising:

forming a passivation layer on the gate insulating layer and the gate electrode.

18. A method of manufacturing a thin film transistor comprising:

forming a gate electrode and a gate insulating layer on a substrate;

forming the channel layer according to claim 11 on the gate insulating layer; and

forming a source electrode and a drain electrode on the channel layer, wherein the source electrode and drain electrode contact ends of the channel layer.

19. The method of claim 18, further comprising:

forming a passivation layer on the gate insulating layer, the channel layer, the source electrode and the drain electrode.

20. A channel layer for a thin film transistor comprising IZO (indium zinc oxide), wherein the entire channel layer is doped with a transition metal, and the channel layer has an electrical conductivity lower than that of an undoped IZO due to the transition metal.

21. The channel layer of claim 20, wherein the transition metal is at least one selected from the elements of Group IX to XI.

22. The channel layer of claim 20, wherein the channel layer is made of a material expressed with an equation of a(In₂O₃).b(ZnO), where a and b are real numbers such that a>

about 0 and b>

about 0.

23. A thin film transistor comprising:

a gate electrode and the channel layer according to claim 20 on a substrate;

a gate insulating layer between the gate electrode and the channel layer; and

a source electrode and a drain electrode which contact ends of the channel layer.