Non-volatile semiconductor storage device with laminated vertical memory cell and select transistors
First Claim
1. A non-volatile semiconductor storage device comprising:
- a substrate;
a control circuit layer provided on the substrate;
a support layer provided entirely above the control circuit layer; and
a memory cell array layer provided on the support layer,the memory cell array layer comprising;
a first semiconductor layer substantially formed in a first direction perpendicular to the substrate;
memory cell transistors formed on the first semiconductor layer,a selection transistor formed on the first semiconductor layer;
the control circuit layer comprising at least one of a row decoder driving word lines and provided below the memory cell array layer, or a sense amplifier sensing and amplifying a signal from bit lines and provided below the memory cell array layer.
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Abstract
A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.
157 Citations
11 Claims
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1. A non-volatile semiconductor storage device comprising:
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a substrate; a control circuit layer provided on the substrate; a support layer provided entirely above the control circuit layer; and a memory cell array layer provided on the support layer, the memory cell array layer comprising; a first semiconductor layer substantially formed in a first direction perpendicular to the substrate; memory cell transistors formed on the first semiconductor layer, a selection transistor formed on the first semiconductor layer; the control circuit layer comprising at least one of a row decoder driving word lines and provided below the memory cell array layer, or a sense amplifier sensing and amplifying a signal from bit lines and provided below the memory cell array layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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- Resources
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Current AssigneeKioxia Corporation
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsIzumi, Tatsuo, Kamigaichi, Takeshi
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Primary Examiner(s)Mandala, Victor A
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Assistant Examiner(s)AHMED, SELIM U
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Application NumberUS13/034,309Publication NumberTime in Patent Office649 DaysField of Search36518517-18518, 365/185.21, 365/185.23, 36518527-18528, 257/315, 257/324, 257/326, 257/331, 257/E29.309, 257/E21.41, 257/E21.679, 257/E27.081US Class Current257/324CPC Class CodesH10B 43/20 characterised by three-dime...H10B 43/27 the channels comprising ver...H10B 43/30 characterised by the memory...H10B 69/00 Erasable-and-programmable R...
