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Dynamic random access memory cell and array having vertical channel transistor

  • US 8,324,682 B2
  • Filed: 02/17/2011
  • Issued: 12/04/2012
  • Est. Priority Date: 12/15/2010
  • Status: Active Grant
First Claim
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1. A dynamic random access memory cell having vertical channel transistor, comprising:

  • a semiconductor pillar disposed in a semiconductor substrate and forming an active region of a vertical channel transistor;

    a drain layer disposed at a bottom of the semiconductor pillar;

    an assisted gate disposed beside the drain layer and separated from the drain layer by a first gate dielectric layer, wherein the assisted gate extends along a first direction;

    a control gate disposed beside the semiconductor pillar and separated from the active region by a second gate dielectric layer, wherein the control gate extends along a second direction, and the second direction is different from the first direction;

    a source layer disposed at a top of the semiconductor pillar; and

    a capacitor electrically connected to the source layer.

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