Dynamic random access memory cell and array having vertical channel transistor

• US 8,324,682 B2
• Filed: 02/17/2011
• Issued: 12/04/2012
• Est. Priority Date: 12/15/2010
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Technology Corporation
• Inventors: Chen, Hui-Huang, Chen, Chih-Yuan, Chen, Chun-Cheng, Yang, Sheng-Fu
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Fan, Michele
• Application Number:
  US13/030,116
• Publication Number:
  US 20120153371A1
• Time in Patent Office: 656 Days
• Field of Search: 257/327, 257/329, 257/365, 257/379, 257/E21.375, 257/E29.255, 257/E29.262, 438/268, 438/270
• US Class Current: 257/327
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.

Claims

1. A dynamic random access memory cell having vertical channel transistor, comprising:

a semiconductor pillar disposed in a semiconductor substrate and forming an active region of a vertical channel transistor;

a drain layer disposed at a bottom of the semiconductor pillar;

an assisted gate disposed beside the drain layer and separated from the drain layer by a first gate dielectric layer, wherein the assisted gate extends along a first direction;

a control gate disposed beside the semiconductor pillar and separated from the active region by a second gate dielectric layer, wherein the control gate extends along a second direction, and the second direction is different from the first direction;

a source layer disposed at a top of the semiconductor pillar; and

a capacitor electrically connected to the source layer.

2. The dynamic random access memory cell having vertical channel transistor as claimed in claim 1, wherein the assisted gate is disposed on two opposite sidewalls of the drain layer.

3. The dynamic random access memory cell having vertical channel transistor as claimed in claim 1, wherein the control gate is disposed on two opposite sidewalls of the semiconductor pillar.

4. The dynamic random access memory cell having vertical channel transistor as claimed in claim 1, wherein the drain layer comprises a doped region.

5. A dynamic random access memory cell array having vertical channel transistor, comprising:

a plurality of memory cells disposed in a semiconductor substrate and arranged into an array of columns and rows, each of the memory cells comprising;

a semiconductor pillar forming an active region of a vertical channel transistor;

a drain layer disposed at a bottom of the semiconductor pillar;

an assisted gate disposed beside the drain layer and separated from the drain layer by a first gate dielectric layer;

a control gate disposed beside the semiconductor pillar and separated from the active region by a second gate dielectric layer;

a source layer disposed at a top of the semiconductor pillar; and

a capacitor electrically connected to the source layer;

a plurality of embedded bit lines disposed in parallel under the semiconductor pillars, extending along a column direction, and electrically connected to the drain layers of a same column;

a plurality of assisted gate lines disposed beside the embedded bit lines and electrically connected to the assisted gates of the same column; and

a plurality of embedded word lines disposed in parallel above the embedded bit lines, extending along a row direction, and electrically connected to the control gates of a same row.

6. The dynamic random access memory cell array having vertical channel transistor as claimed in claim 5, wherein each of the embedded bit lines is disposed between two adjacent assisted gate lines.

7. The dynamic random access memory cell array having vertical channel transistor as claimed in claim 5, wherein the embedded word lines are disposed on two opposite sidewalls of each of the semiconductor pillars respectively.

8. The dynamic random access memory cell having vertical channel transistor as claimed in claim 5, wherein each of the embedded bit lines comprises a doped region.

9. The dynamic random access memory cell array having vertical channel transistor as claimed in claim 5, wherein the assisted gate lines are electrically connected to one another.