Dynamic random access memory cell and array having vertical channel transistor
First Claim
1. A dynamic random access memory cell having vertical channel transistor, comprising:
- a semiconductor pillar disposed in a semiconductor substrate and forming an active region of a vertical channel transistor;
a drain layer disposed at a bottom of the semiconductor pillar;
an assisted gate disposed beside the drain layer and separated from the drain layer by a first gate dielectric layer, wherein the assisted gate extends along a first direction;
a control gate disposed beside the semiconductor pillar and separated from the active region by a second gate dielectric layer, wherein the control gate extends along a second direction, and the second direction is different from the first direction;
a source layer disposed at a top of the semiconductor pillar; and
a capacitor electrically connected to the source layer.
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Accused Products
Abstract
A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.
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Citations
9 Claims
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1. A dynamic random access memory cell having vertical channel transistor, comprising:
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a semiconductor pillar disposed in a semiconductor substrate and forming an active region of a vertical channel transistor; a drain layer disposed at a bottom of the semiconductor pillar; an assisted gate disposed beside the drain layer and separated from the drain layer by a first gate dielectric layer, wherein the assisted gate extends along a first direction; a control gate disposed beside the semiconductor pillar and separated from the active region by a second gate dielectric layer, wherein the control gate extends along a second direction, and the second direction is different from the first direction; a source layer disposed at a top of the semiconductor pillar; and a capacitor electrically connected to the source layer. - View Dependent Claims (2, 3, 4)
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5. A dynamic random access memory cell array having vertical channel transistor, comprising:
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a plurality of memory cells disposed in a semiconductor substrate and arranged into an array of columns and rows, each of the memory cells comprising; a semiconductor pillar forming an active region of a vertical channel transistor; a drain layer disposed at a bottom of the semiconductor pillar; an assisted gate disposed beside the drain layer and separated from the drain layer by a first gate dielectric layer; a control gate disposed beside the semiconductor pillar and separated from the active region by a second gate dielectric layer; a source layer disposed at a top of the semiconductor pillar; and a capacitor electrically connected to the source layer; a plurality of embedded bit lines disposed in parallel under the semiconductor pillars, extending along a column direction, and electrically connected to the drain layers of a same column; a plurality of assisted gate lines disposed beside the embedded bit lines and electrically connected to the assisted gates of the same column; and a plurality of embedded word lines disposed in parallel above the embedded bit lines, extending along a row direction, and electrically connected to the control gates of a same row. - View Dependent Claims (6, 7, 8, 9)
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Specification