Semiconductor device and a method of manufacturing the same

• US 8,324,706 B2
• Filed: 06/10/2010
• Issued: 12/04/2012
• Est. Priority Date: 09/15/2005
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yoshizumi, Keiichi, Higuchi, Kazuhisa, Nakaji, Takayuki, Koketsu, Masami, Yasuoka, Hideki
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US12/813,144
• Publication Number:
  US 20100244137A1
• Time in Patent Office: 908 Days
• Field of Search: 257/173, 257355-360, 257/500
• US Class Current: 257/500
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a MISFET formed over the semiconductor substrate;

a trench formed in the semiconductor substrate;

a first insulating film buried in the trench; and

a plurality of dummy active regions defined by the trench,

wherein the dummy active regions are regions where the MISFETS is not formed,

wherein second insulating film portions are formed over the dummy active regions,

wherein a resistance element is formed over the second insulating film portions,

wherein the dummy active regions are located under the resistance element,

wherein a third insulating film is formed on the resistance element,

wherein the resistance element has first, second, and third portions,

wherein the first portion and the second portion are exposed from the third insulating film,

wherein the third portion is covered with the third insulating film,

wherein a first silicide layer is formed on the first portion and a second silicide layer is formed on the second portion,

wherein, in a plan view, opposite sides of the resistance element are located over the first insulating film,

wherein, in a plan view, a part of the first silicide layer and a part of the second silicide layer are located

over the first insulating film, and wherein the first insulating film is thicker than the second insulating film portions.

2. A semiconductor device according to claim 1,

wherein the second insulating film portions are a silicon oxide film formed by chemical vapor deposition.

3. A semiconductor device according to claim 1,

wherein the resistance element is formed of a silicon film.

4. A semiconductor device according to claim 1,

wherein the dummy active regions are formed in an island or lattice or matrix pattern.

5. A semiconductor device according to claim 1,

wherein, in a plan view, an edge of the resistance element is not located over the dummy active regions.

6. A semiconductor device according to claim 1,

wherein the resistance element is used for a part of an ESD protection circuit.

7. A semiconductor device according to claim 6,

wherein the semiconductor device is applied to an LCD driver.

8. A semiconductor device according to the claim 1, further comprising:

a first MISFET having a gate insulating film and a gate electrode,

wherein the gate insulating film and the second insulating film portions are formed as the same layer.

25. A semiconductor device according to the claim 1,

wherein the second insulating film portions are formed to be portions of a continuous film that has additional portions formed over portions of said first insulating film.

9. A semiconductor device comprising:

a semiconductor substrate;

a trench formed in the semiconductor substrate;

a first insulating film buried in the trench;

a plurality of predetermined regions defined by the trench; and

second insulating film portions formed over the predetermined regions,

wherein a resistance element is formed over the second insulating film portions and is overlapped with the predetermined regions,

wherein a third insulating film is formed on the resistance element,

wherein the resistance element has a first portion exposed from the third insulating film and a second portion covered with the third insulating film,

wherein a first silicide layer is formed on the first portion,

wherein edge portions of the resistance element are disposed over the first insulating film in a plan view,

wherein a part of the first silicide layer is disposed over the first insulating film in a plan view, and

wherein the first insulating film is thicker than the second insulating film portions.

10. A semiconductor device according to claim 9,

wherein the second insulating film portions are a silicon oxide film formed by chemical vapor deposition.

11. A semiconductor device according to claim 9, wherein the resistance element is formed of a silicon film.

12. A semiconductor device according to claim 9, wherein the predetermined regions are formed in an island or lattice or matrix pattern.

13. A semiconductor device according to claim 9, wherein, in a plan view, said edge portions of the resistance element are not located over the predetermined regions.

14. A semiconductor device according to claim 9, wherein the resistance element is used for a part of an ESD protection circuit.

15. A semiconductor device according to claim 14, wherein the semiconductor device is applied to an LCD driver.

16. A semiconductor device according to the claim 9, further comprising:

a MISFET having a gate insulating film and a gate electrode,

wherein the gate insulating film and the second insulating film portions are formed as the same layer, and

wherein the gate electrode and the resistance element are formed as the same layer.

17. A semiconductor device according to claim 9, wherein the resistance element is located between an input/output terminal and an internal circuit.

18. A semiconductor device according to the claim 9,

wherein the predetermined regions are dummy active regions.

19. A semiconductor device according to the claim 18, further comprising:

a MISFET formed over the semiconductor substrate, wherein the dummy active regions are regions where the MISFET is not formed.

20. A semiconductor device according to the claim 18,

wherein the dummy active regions are formed so as to prevent concaving of the first insulating film.

21. A semiconductor device according to the claim 9,

wherein the resistance element is rectangular in shape,

wherein a length of a first edge portion of the resistance element is shorter than a length of a second edge portion of the resistance element, and

wherein the first edge portion is disposed over the first insulating film in a plan view.

22. A semiconductor device according to the claim 21,

wherein the resistance element further comprises a third edge portion,

wherein a length of a third edge portion is equal to the length of the first edge portion,

wherein the resistance element has a third portion exposed from the third insulating film,

wherein a second silicide layer is formed on the third portion,

wherein the third edge portion is disposed over the first insulating film in a plan view, and

wherein a part of the second silicide layer is disposed over the first insulating film in a plan view.

23. A semiconductor device according to the claim 9,

wherein said edge portions of the resistance element disposed over the first insulating film are at opposite sides of the resistance element.

24. A semiconductor device according to the claim 9,

wherein the second insulating film portions are formed to be portions of a continuous film that has additional portions formed over portions of said first insulating film.