Semiconductor device comprising a through electrode and a pad connected to the through electrode and having an exposed portion and method for fabricating the same

• US 8,324,733 B2
• Filed: 03/22/2010
• Issued: 12/04/2012
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, In Young, Jang, Donghyeon, Kim, Namseog
• Primary Examiner(s): Williams, A O
• Application Number:
  US12/728,683
• Publication Number:
  US 20100252935A1
• Time in Patent Office: 988 Days
• Field of Search: 257/773, 257/777, 257/723, 257/686, 257/685, 257/E21.522, 257/E23.011, 257/E21.577, 257/690, 257/E23.174, 257/E25.013, 257/E23.169, 257/737, 257/738, 257/734, 257/666, 257/E25.027, 257/E23.145, 257/E21.585, 257/620, 257/E23.179, 257/698, 257/692, 257/E23.176, 257/E23.141
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06505 Bonding areas having different materials
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14505 Bump connectors having different materials
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/17505 Bump connectors having different materials
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48105 Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor device and a method for fabricating the same, wherein a portion of a substrate comprising a pad is removed to form a via hole. An insulating layer is formed on the substrate. A portion of the insulating layer is removed to form a plurality of openings exposing portions of the pad. A through electrode is formed to fill the via hole and to be electrically connected to the pad through one of the plurality of openings. A portion of the pad is exposed by another opening among the plurality of openings.

Claims

1. A semiconductor device comprising:

a substrate having a front side on which a pad is disposed and a backside opposite to the front side, the substrate having a via hole penetrating therethrough;

a through electrode at least partially filling the via hole and having an upper end protruding from the front side; and

an insulating layer to insulate the through electrode from the substrate, the insulating layer comprising a first opening extending through the insulating layer, through which a portion of the pad is connected to the through electrode, and a second opening exposing another portion of the pad, wherein the first opening exposes a first portion of the pad adjacent to the through electrode, the second opening exposes a second portion of the pad spaced apart from the through electrode, and the first and second portions of the pad extend from each other to be connected to each other in a continuous structure.

2. The semiconductor device of claim 1, wherein a portion of the through electrode extends through the first opening and is connected to the exposed first portion of the pad, and wherein an external terminal is connected to the second portion of the pad through the second opening.

3. The semiconductor device of claim 2, wherein the pad comprises:

a through electrode pad comprising the first portion of the pad to be connected to the through electrode; and

a bonding pad comprising the second portion of the pad to be connected to the external terminal.

4. The semiconductor device of claim 1, wherein the insulating layer comprises:

a passivation layer covering the pad; and

a via hole insulating layer covering the passivation layer and an inner surface of the via hole.

5. The semiconductor device of claim 1, wherein the insulating layer comprises a passivation layer covering the pad and an inner surface of the via hole.

6. The semiconductor device of claim 1, further comprising a solder on the through electrode, the solder being in self-alignment with the through electrode, wherein the solder covers an entire surface of the through electrode.

7. A semiconductor device comprising:

a first semiconductor chip comprising a first through electrode and a first pad connected to the first through electrode, a first portion and a second portion of the first pad being exposed through separate openings in an insulating layer on the first semiconductor chip, wherein the first and second portions of the pad extend from each other to be connected to each other in a continuous structure; and

a second semiconductor chip stacked on the first semiconductor chip and comprising a second through electrode and a second pad connected to the second through electrode, a portion of the second pad being exposed,

wherein the first and second through electrodes are connected to electrically connect the first and second semiconductor chips to each other.

8. The semiconductor device of claim 7, further comprising a connection terminal that electrically connects the first pad to the second pad.

9. The semiconductor device of claim 8, further comprising a third semiconductor chip stacked on the second semiconductor chip,

wherein the second and third semiconductor chips are electrically connected by at least one of the connection terminal connected to the second pad and the second through electrode.

10. The semiconductor device of claim 8, further comprising a printed circuit board on which the first semiconductor chip is disposed,

wherein the first semiconductor chip and the printed circuit board are electrically connected by at least one of the first through electrode and the connection terminal connected to the first pad.

11. The semiconductor device of claim 7, further comprising a solder on the first through electrode, the solder being in self-alignment with the first through electrode, wherein the solder covers an entire surface of the first through electrode.