Self-aligned protection layer for copper post structure

• US 8,324,738 B2
• Filed: 05/25/2010
• Issued: 12/04/2012
• Est. Priority Date: 09/01/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chung-Shi, Yu, Chen-Hua
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US12/786,698
• Publication Number:
  US 20110049705A1
• Time in Patent Office: 924 Days
• Field of Search: 257779-781, 438/612, 438/613, 438/614, 438/666
• US Class Current: 257/781
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01043 : Technetium [Tc]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A copper post is formed in a passivation layer to electrically connect an underlying bond pad region, and extends to protrude from the passivation layer. A protection layer is formed on a sidewall surface or a top surface of the copper post in a self-aligned manner. The protection layer is a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a bond pad region on the semiconductor substrate;

a copper-containing post overlying and electrically connected to the bond pad region; and

a protection layer on a surface of the copper-containing post, wherein the protection layer comprises manganese (Mn).

2. The semiconductor device of claim 1, wherein the protection layer is an oxide layer comprising manganese.

3. The semiconductor device of claim 1, wherein the protection layer is a nitride layer comprising manganese.

4. The semiconductor device of claim 1, wherein the protection layer is an oxynitride layer comprising manganese.

5. The semiconductor device of claim 1, wherein the copper-containing post comprises a top surface and a sidewall surface, wherein the protection layer is formed on the sidewall surface of the copper-containing post.

6. The semiconductor device of claim 5, wherein the protection layer is formed on the top surface of the copper-containing post.

7. The semiconductor device of claim 5, further comprising a cap layer formed on the top surface of the copper-containing post.

8. The semiconductor device of claim 7, wherein the cap layer comprises at least one of tin, silver, nickel, gold or combinations thereof.

9. The semiconductor device of claim 1, further comprising

a passivation layer overlying the semiconductor substrate and exposing a portion of the bond pad region, wherein

the copper-containing post is formed in the passivation layer and overlying the exposed portion of the bond pad region, and

the copper-containing post extends to protrude from the passivation layer;

and

an under-bump metallurgy (UBM) layer formed between the bond pad region and the copper-containing post.

10. The semiconductor device of claim 1, further comprising

a passivation layer overlying the semiconductor substrate and exposing a portion of the bond pad region;

an interconnect line formed overlying the passivation layer and the exposed portion of the bond pad region, wherein the interconnect line is electrically connected to bond pad region;

a polymer layer formed overlying the interconnect line and exposing a portion of the interconnect line, wherein

the copper-containing post is formed in the polymer layer and extends to protrude from the polymer layer, and

the copper-containing post is formed overlying and electrically connected to the exposed portion of the interconnect line; and

an under-bump metallurgy (UBM) layer formed between the interconnect line and the copper-containing post.

11. The semiconductor device of claim 10, further comprising a dielectric layer formed between the polymer layer and the interconnect line, and formed between the polymer layer and the passivation layer.

12. The semiconductor device of claim 11, wherein the dielectric layer comprises a silicon nitride layer.

13. The semiconductor device of claim 10, wherein the interconnect line comprises copper.

14. The semiconductor device of claim 10, wherein the polymer layer comprises polyimide.

15. The semiconductor device of claim 10, further comprising an adhesion layer formed between the passivation layer and the interconnect line.

16. The semiconductor device of claim 15, wherein the adhesion layer comprises at least one of titanium, copper or combinations thereof.

17. A semiconductor device, comprising:

a semiconductor substrate;

a conductive region on the semiconductor substrate;

a passivation layer on the semiconductor substrate and having a first opening exposing a portion of the conductive region;

an interconnect line overlying the passivation layer and filling the first opening, electrically connected to the conductive region;

a polymer layer overlying the interconnect line and having a second opening exposing a portion of the interconnect line;

a copper post formed in the second opening electrically connected to the interconnect line and protruding from the polymer layer; and

a protection layer formed on a sidewall surface of the copper post, wherein the protection layer comprises a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer.

18. The semiconductor device of claim 17, further comprising a cap layer on a top surface of the copper post.

20. The semiconductor device of claim 17, further comprising a cap layer on a top surface of the copper post.

19. A semiconductor device, comprising:

a semiconductor substrate;

a conductive region on the semiconductor substrate;

a passivation layer on the semiconductor substrate and having an opening exposing a portion of the conductive region;

a copper post formed in the opening and electrically connected to the conductive region, and protruding from the passivation layer; and

a protection layer formed on a sidewall surface of the copper post, wherein the protection layer comprises a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer.