Automatic on-chip detection of power supply configuration-modes for integrated chips

• US 8,324,756 B2
• Filed: 10/06/2008
• Issued: 12/04/2012
• Est. Priority Date: 10/06/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dash, Ranjit Kumar, Balasubramanian, Lakshmanan, Kudari, Anand Devendra
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): Fauth, Justen
• Application Number:
  US12/245,776
• Publication Number:
  US 20100085087A1
• Time in Patent Office: 1,520 Days
• Field of Search: None
• US Class Current: 307/31
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575

Abstract

A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.

Claims

1. An integrated circuit device capable of being powered by either an internal power supply or an external power supply, comprising:

an internal power supply;

a node coupled to the internal power supply and capable of being coupled to an external power supply;

a power management system for detecting whether an external power supply is coupled to said node during start-up of the integrated circuit device prior to enabling the internal power supply, the power management system including;

a discharge circuit for discharging the node for a predetermined discharge time during start-up of the integrated circuit;

a comparator coupled to the node for determining during the predetermined discharge time whether the node is driven by an external power supply and providing a first output signal when the node is driven by an external power supply and a second output signal when the node is not driven by an external power supply.

2. The integrated circuit device of claim 1, wherein the internal power supply is a low dropout regulator (LDO).

3. The integrated circuit device of claim 1, wherein the internal power supply is not enabled during start-up of the integrated circuit device when the comparator provides the first output signal in response to the node being driven by an external power supply and is enabled during start-up of the integrated circuit device when the comparator provides the second output signal in response to the node not being driven by an external power supply.