Post-programming functional verification for programable integrated circuits
First Claim
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1. A computer-implemented method for performing verification of an integrated circuit, the method comprising:
- identifying an integrated circuit, the integrated circuit including a plurality of input/output pins and a verification component;
identifying a verification test, the verification test defining a signal and at least one of the plurality of input/output pins;
sending the verification test to the verification component;
causing the verification component to load the verification test onto the at least one of the plurality of input/output pins;
causing the integrated circuit to process at least one clock cycle;
causing the verification component to capture the states of the plurality of input/output pins;
receiving the states of the plurality of input/output pins.
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Abstract
Techniques and technology are provided to enable the testing of a programmable integrated circuit from within the programmable integrated circuit itself. In various implementations of the invention, a hardware verification module is added to the programmable integrated circuit by the manufacturer. Once the programmable integrated circuit is programmed to have a desired functionality, the hardware verification module may be activated and used to apply tests and receive responses from the programmable integrated circuit to verify its functionality.
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Citations
17 Claims
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1. A computer-implemented method for performing verification of an integrated circuit, the method comprising:
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identifying an integrated circuit, the integrated circuit including a plurality of input/output pins and a verification component; identifying a verification test, the verification test defining a signal and at least one of the plurality of input/output pins; sending the verification test to the verification component; causing the verification component to load the verification test onto the at least one of the plurality of input/output pins; causing the integrated circuit to process at least one clock cycle; causing the verification component to capture the states of the plurality of input/output pins; receiving the states of the plurality of input/output pins.
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2. A computer-implemented method for performing verification of a programmable integrated circuit, the method comprising:
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identifying a programmable integrated circuit, the programmable integrated circuit including a plurality of input/output pins and a verification component; identifying a verification test; sending the verification test to the verification component; causing the verification component to load the verification test onto the at least one of the plurality of input/output pins; causing the programmable integrated circuit to process at least one clock cycle; causing the verification component to capture the states of the plurality of input/output pins; and receiving the states of the plurality of input/output pins from the verification component. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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9. One or more non-transitory computer-readable media, having computer executable instructions for performing verification of a programmable integrated circuit stored thereon, the computer executable instructions comprising:
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causing a computer to perform a set of operations; and wherein the set of operations include; identifying a programmable integrated circuit, the programmable integrated circuit including a plurality of input/output pins and a verification component; identifying a verification test; sending the verification test to the verification component; causing the verification component to load the verification test onto the at least one of the plurality of input/output pins; causing the programmable integrated circuit to process at least one clock cycle; causing the verification component to capture the states of the plurality of input/output pins; and receiving the states of the plurality of input/output pins from the verification component. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An apparatus for verifying a programmable integrated circuit comprising:
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an input/output port driver module configured to connect to a programmable integrated circuit, the programmable integrated circuit having a plurality of input/output pins and a verification component; a test set generation module configured to receive a verification test set, the verification test set including; one or more input signal names; one or more input signal states corresponding to the one or more input signal names; one or more output signal names; and one or more expected output signal states corresponding to the one or more output signal names; a test set mapping module configured to receive a pin mapping and then identify one or more of the input/output pins corresponding to a one of the signal names; and a test set application module configured to; send the verification test to the verification component; causes the verification component to load the verification test onto the at least one of the plurality of input/output pins; cause the programmable integrated circuit to process at least one clock cycle; cause the verification component to capture the states of the plurality of input/output pins; and receive the captured states from the verification component. - View Dependent Claims (17)
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Specification