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High speed multiple memory interface I/O cell

  • US 8,324,927 B2
  • Filed: 12/16/2010
  • Issued: 12/04/2012
  • Est. Priority Date: 10/09/2007
  • Status: Expired due to Fees
First Claim
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1. A binary programmable predriver comprising:

  • a plurality of first drivers, each first driver comprising a programmable binary weighted cascode ngate driver; and

    a plurality of second drivers, each second driver comprising a programmable binary weighted cascode pgate driver, wherein said binary programmable predriver is configured to generate a first driver control signal and a second driver control signal in response to a drive control signal, an on-die termination control signal, a slew control signal, and a data output signal.

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