High speed multiple memory interface I/O cell

• US 8,324,927 B2
• Filed: 12/16/2010
• Issued: 12/04/2012
• Est. Priority Date: 10/09/2007
• Status: Expired due to Fees

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Bhakta, Dharmesh, Lim, Hong-Him, Kong, Cheng-Gang, Randazzo, Todd
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): Tran, Jany
• Application Number:
  US12/970,071
• Publication Number:
  US 20110084725A1
• Time in Patent Office: 719 Days
• Field of Search: 326/30, 326/35, 326/62, 326 83- 83, 326 86- 87
• US Class Current: 326/30
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Claims

1. A binary programmable predriver comprising:

a plurality of first drivers, each first driver comprising a programmable binary weighted cascode ngate driver; and

a plurality of second drivers, each second driver comprising a programmable binary weighted cascode pgate driver, wherein said binary programmable predriver is configured to generate a first driver control signal and a second driver control signal in response to a drive control signal, an on-die termination control signal, a slew control signal, and a data output signal.

2. The binary programmable predriver according to claim 1, wherein said programmable binary weighted cascode ngate driver comprises a programmable 5-bit binary weighted cascode driver and each of said plurality of first drivers further comprises:

a multiplexer circuit; and

a NAND data path.

3. The binary programmable predriver according to claim 1, wherein said programmable binary weighted cascode pgate driver comprises a programmable 5-bit binary weighted cascode driver and each of said plurality of second drivers further comprises:

a multiplexer circuit; and

a NOR data path.

4. The binary programmable predriver according to claim 1, further comprising:

a data enable logic; and

an on-die termination (ODT) sequencer.

5. The binary programmable predriver according to claim 4, wherein said ODT sequencer provides dynamic switching between an input/output mode and a termination mode.

6. The binary programmable predriver according to claim 1, further comprising a dynamic on-die termination (ODT) sequencer comprising:

a first circuit configured to generate an on-die termination mode control signal in response to an enable signal and a termination control signal; and

a second circuit configured to generate a driver mode control signal in response to the enable signal and the termination control signal.

7. The binary programmable predriver according to claim 6, wherein said first circuit comprises a NAND-NOR tree and said second circuit comprises a NOR-NAND tree.

8. The binary programmable predriver according to claim 6, wherein the dynamic on-die termination (ODT) sequencer further comprises:

a third circuit configured to generate a first sequencer output signal and a second sequencer output signal in response to the enable signal, the termination control signal, and the data output signal.

9. The binary programmable predriver according to claim 1, wherein said programmable binary weighted cascode ngate driver comprises a 5-bit digital-to-current (D-I) converter.

10. The binary programmable predriver according to claim 9, wherein said 5-bit digital-to-current (D-I) converter is configured to generate a first driver control signal in response to a slew control signal and a signal combining the data output signal with either driver or on-die termination code information.

11. The binary programmable predriver according to claim 9, wherein said 5-bit digital-to-current (D-I) converter comprises:

a first stage comprising a plurality of transistors having a first channel width and a plurality of transistors having a second channel width, wherein said first channel width and said second channel width have a ratio of 2;

1;

a second stage comprising a plurality of transistors having said second channel width and a plurality of transistors having a third channel width, wherein said second channel width and said third channel width have a ratio of 2;

1;

a third stage comprising a plurality of transistors having said third channel width and a plurality of transistors having a fourth channel width, wherein said third channel width and said fourth channel width have a ratio of 2;

1; and

a fourth stage comprising a plurality of transistors having said fourth channel width and connected in parallel and a plurality of transistors having said fourth channel width and connected to form a cascode.

12. The binary programmable predriver according to claim 1, wherein said programmable binary weighted cascode pgate driver comprises a 5-bit digital-to-current (D-I) converter.

13. The binary programmable predriver according to claim 12, wherein said 5-bit digital-to-current (D-I) converter is configured to generate a second driver control signal in response to a slew control signal and a signal combining the data output signal with either driver or on-die termination code information.

14. The binary programmable predriver according to claim 12, wherein said 5-bit digital-to-current (D-I) converter comprises:

a first stage comprising a plurality of transistors having a first channel width and a plurality of transistors having a second channel width;

a second stage comprising a plurality of transistors having said first channel width and a plurality of transistors having a third channel width, wherein said second channel width and said third channel width have a ratio of 2;

1;

a third stage comprising a plurality of transistors having said first channel width and a plurality of transistors having a fourth channel width, wherein said third channel width and said fourth channel width have a ratio of 2;

1; and

a fourth stage comprising a plurality of transistors having said fourth channel width and a plurality of transistors having a fifth channel width, wherein said first channel width and said fifth channel width have a ratio of 2;

1.

15. The binary programmable predriver according to claim 1, wherein said programmable binary weighted cascode ngate driver comprises:

a plurality of first p-channel transistors connected to power and controlled by an input signal;

a plurality of second p-channel transistors each connected between an output node of said cascode ngate driver and a respective one of said first p-channel transistors and controlled by a first control signal;

a plurality of first n-channel transistors connected to ground and controlled by said input signal; and

a plurality of second n-channel transistors each connected between said output node of said cascode ngate driver and a respective one of said first n-channel transistors and controlled by a second control signal.

16. The binary programmable predriver according to claim 1, wherein said programmable binary weighted cascode pgate driver comprises:

a plurality of first p-channel transistors connected to power and controlled by an input signal;

a plurality of second p-channel transistors each connected between an output node of said cascode pgate driver and a respective one of said first p-channel transistors and controlled by a first control signal;

a plurality of first n-channel transistors connected to ground and controlled by said input signal; and

a plurality of second n-channel transistors each connected between said output node of said cascade pgate driver and a respective one of said first n-channel transistors and controlled by a second control signal.

17. A dynamic on-die termination sequencer comprising:

a first circuit configured to generate a on-die termination mode control signal in response to an enable signal and a termination control signal,

a second circuit configured to generate a driver mode control signal in response to the enable signal and the termination control signal; and

a third circuit configured to generate a first sequencer output signal and a second sequencer output signal in response to the enable signal, the termination control signal, and a data output signal.

18. The dynamic on-die termination sequencer according to claim 17, wherein said first circuit comprises a NAND-NOR tree and said second circuit comprises a NOR-NAND tree.

19. The dynamic on-die termination sequencer according to claim 17, wherein said dynamic on-die termination sequencer is configured to turn on-die termination on and off in response to the enable signal and the termination control signal such that both pull-up and pull-down terminations are not on when a driver mode is enabled.

20. A dynamic on-die termination sequencer comprising:

a first circuit configured to generate a on-die termination mode control signal in response to an enable signal and a termination control signal; and

a second circuit configured to generate a driver mode control signal in response to the enable signal and the termination control signal, wherein said first circuit comprises a NAND-NOR tree and said second circuit comprises a NOR-NAND tree.