Level shifter design

• US 8,324,955 B2
• Filed: 03/18/2011
• Issued: 12/04/2012
• Est. Priority Date: 03/18/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Roth, Alan, Hsu, Ying-Chih, Shi, Justin, Soenen, Eric
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Hernandez, William
• Application Number:
  US13/051,343
• Publication Number:
  US 20120235728A1
• Time in Patent Office: 627 Days
• Field of Search: 326/62, 326/63, 326/68, 326/80, 326/81, 327/333, 365/189.11
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.

Claims

1. A level shifter configured to receive an input voltage signal and produce an output voltage signal comprising:

a first inverter, configured to operate at a potential difference between a first voltage V1 received at a voltage V1 signal node and a second voltage V2 received at a voltage V2 signal node, the first inverter having an input terminal connected to an input node of the level shifter, and further having an output terminal;

a capacitor having a first terminal connected to the output terminal of the first inverter, and further having a second terminal;

a resistor having a first terminal connected to a third voltage V3 at a voltage V3 signal node and a second terminal; and

a latch circuit, configured to operate at a potential difference between a fourth voltage V4 received at a voltage V4 signal node and a fifth voltage V5 received at a voltage V5 signal node, the latch having an input node connected to the second terminal of the resistor and the second terminal of the capacitor, and further having an output node connected to an output node of the level shifter.

2. The level shifter of claim 1, wherein a value of the input voltage signal of the level shifter is between a value of the voltage V1 and a value of the voltage V2, and a value of the output voltage signal of the level shifter is between a value of the voltage V4 and a value of the voltage V5.

3. The level shifter of claim 1, wherein the latch circuit has a plurality of inverters including a first latch inverter and a second latch inverter, wherein an output terminal of the first latch inverter is connected to an input terminal of the second latch inverter while an output terminal of the second latch inverter is connected to an input terminal of the first latch inverter.

4. The level shifter of claim 1, wherein a value of the voltage V4 is less than twice value of the voltage V1 minus a value of the voltage V5 while larger than V5.

5. The level shifter of claim 1, wherein a value of the voltage V3 can selectively be the same as a value of the voltage V4, or as a value of the voltage V5.

6. The level shifter of claim 1, wherein a value of the voltage V1 is the same as a value of the voltage V4.

7. The level shifter of claim 1, wherein a value of the voltage V2 is the same as a value of the voltage V5.

8. The level shifter of claim 1 further comprising a P-transistor, wherein the voltage V5 signal node is connected to a first terminal of the P-transistor while a second terminal of the P-transistor is connected to a sixth voltage V6 signal node, and a gate of the P-transistor is connected to a seventh voltage V7 signal node.

9. The level shifter of claim 1 further comprising an N-transistor, wherein the voltage V4 signal node is connected to a first terminal of the N-transistor while a second terminal of the N-transistor is connected to a sixth voltage V6 signal node, and a gate of the N-transistor is connected to a seventh voltage V7 signal node.

10. A device configured to receive a first input voltage signal at a first input node and a second input voltage signal at a second input node, and further produce an output comprising:

a first inverter, configured to operate at a potential difference between a first voltage VP1 of the first inverter at a voltage VP1 signal node and a second voltage VP2 of the first inverter at a voltage VP2 signal node, the first inverter having an input terminal connected to the first input node of the device, and further having an output terminal;

a first capacitor having a first terminal connected to the output terminal of the first inverter, and a second terminal;

a first resistor having a first terminal connected to a third voltage VP3 of the first resistor at a voltage VP3 signal node and a second terminal;

a first latch circuit, configured to operate at a potential difference between a fourth voltage VP4 of the first latch at a voltage VP4 signal node and a fifth voltage VP5 of the first latch at a voltage VP5 signal node, the latch having an input node connected to the second terminal of the first resistor and the second terminal of the first capacitor, and an output node;

a first P-transistor, wherein the voltage VP5 signal node is connected to a first terminal of the first P-transistor while a second terminal of the first P-transistor is connected to a sixth voltage VP6 signal node of the first P-transistor, and a gate of the first P-transistor is connected to a seventh voltage VP7 signal node of the first P-transistor;

a first latch output inverter with an input terminal connected to the output terminal of the first latch, and an output terminal, driven by voltages V8 and V9 at a voltage V8 signal node and a voltage V9 signal node respectively;

a second P-transistor with its gate connected to the output terminal of the first latch output inverter, its first terminal connected a voltage V12 signal node, and its second terminal connected to the output of the device;

a second inverter, configured to operate at a potential difference between a first voltage VN1 of the second inverter at a voltage VN1 signal node and a second voltage VN2 of the second inverter at a voltage VN2 signal node, the second inverter having an input terminal connected to a second input node of the device, and further having an output terminal;

a second capacitor having a first terminal connected to the output terminal of the second inverter, and a second terminal;

a second resistor having a first terminal connected to a third voltage VN3 of the second transistor at a voltage VN3 signal node and a second terminal;

a second latch circuit, configured to operate at a potential difference between a fourth voltage VN4 of the second latch at a voltage VN4 signal node and a fifth voltage VN5 of the second latch at a voltage VN5 signal node, and further having an input node connected to the second terminal of the second resistor and the second terminal of the second capacitor, and an output node;

a first N-transistor, wherein the voltage VN4 signal node is connected to a first terminal of the first N-transistor while a second terminal of the first N-transistor is connected to a sixth voltage VN6 signal node of the first N-transistor, and a gate of the first N-transistor is connected to a seventh voltage VN7 signal node of the first N-transistor;

a second latch output inverter with an input terminal connected to the output of the second latch and an output terminal, driven by voltages V10 and V11 at a voltage V10 signal node and a voltage V11 signal node respectively; and

a second N-transistor with its gate connected to the output terminal of the second latch output inverter, its first terminal connected a voltage V13 signal node, and its second terminal connected to the output of the device.

11. The device of claim 10, wherein the first input voltage signal node of the device connected to the first inverter is the same as the second input voltage signal node of the device connected to the second inverter.

12. The device of claim 11, wherein the first inverter is the same as the second inverter.

13. The device of claim 10, wherein the voltage VN1 signal node and the voltage VN4 signal node are the same;

and the voltage VN2 signal node, the voltage VN3 signal node, and the voltage VN5 are the same.

14. The device of claim 10, wherein the voltage VP4 signal node and the voltage VP3 signal node are the same, while the voltage VP6 signal node and the voltage VP2 signal node are the same.

15. The device of claim 10, wherein the voltage VP1 signal node and the voltage VN1 signal node are the same.

16. The device of claim 10, wherein the voltage V8 signal node and V12 signal node are the same as the voltage VP4 signal node.

17. The device of claim 10, wherein the first input voltage signal of the device received by the first inverter has a non-overlapping phase from the second input voltage signal of the device received by the second inverter.

18. A method of operating a level shifter circuit configured to receive an input voltage signal and produce an output voltage signal comprising:

receiving the input voltage signal by a first inverter operating at a potential difference between a first voltage V1 and a second voltage V2 and inverting the input voltage signal, with an output terminal connected to a first terminal of a capacitor;

capacitively coupling the inverted input voltage signal by the capacitor to an input of a latch circuit;

maintaining a desired voltage on the input of the latch by coupling the input of the latch to a voltage source via a resistor; and

generating the output voltage signal by the latch operating at a potential difference between a fourth voltage V4 and a fifth voltage V5.

19. The method of claim 18, further comprising:

connecting selectively either the fifth voltage V5 signal or the fourth voltage V4 signal to a first terminal of an extension transistor while connecting a second terminal of the extension transistor to a sixth voltage signal, and controlling a gate of the extension transistor by a seventh voltage signal.

20. The method of claim 19, further comprising:

receiving by a first component level shifter which operates according to the method of claim 19 to receive a first input voltage signal, and producing an output voltage signal of the first component level shifter, wherein the extension transistor is a P-transistor and the voltage V5 of the first component level shifter is connected to a first terminal of the P-transistor;

receiving by a first inverter driven by voltages V8 and V9 the output voltage signal of the first component level shifter and producing an output of the first inverter;

receiving by a second P-transistor the output of the first inverter, wherein the second P-transistor has its first terminal connected a voltage V12, and its second terminal connected to a first output voltage;

receiving a second input voltage signal by a second component level shifter operating according to the method of claim 19, wherein the extension transistor is an N-transistor and the voltage V4 of the second component level shifter is connected to a first terminal of the N-transistor;

receiving by a second inverter driven by voltages V10 and V11 the output voltage signal of the second component level shifter; and

receiving by a second N-transistor with its gate connected to the output terminal of the second inverter, its first terminal connected a voltage V13, and its second terminal connected to the first output voltage.

21. The method of claim 20, wherein:

the P-transistors and N-transistors are drain-extended devices respectively.