Radio frequency identification transponder

• US 8,325,016 B2
• Filed: 10/30/2007
• Issued: 12/04/2012
• Est. Priority Date: 02/28/2000
• Status: Active Grant

• Current Assignee: SATO Holdings Corporation
• Original Assignee: Magellan Technology Pty. Ltd (SATO Holdings Corporation)
• Inventors: Littlechild, Stuart Colin, Stanton, Michael John
• Primary Examiner(s): Nguyen, Nam V
• Application Number:
  US11/928,357
• Publication Number:
  US 20080197976A1
• Time in Patent Office: 1,862 Days
• Field of Search: 340/10.2, 340/10.32, 340/10.34, 340/10.51, 340/541, 235/375, 235/384
• US Class Current: 340/10.2
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A radio frequency identification transponder includes a power supply and a dynamic memory array that stores data. When power from the power supply ceases, the data in the dynamic memory array is validly maintained for a predetermined period of time. The dynamic memory array is responsive to an interrogating signal for selectively updating the data. A radio frequency identification transponder includes a signal processor that extracts an identifier from the interrogation signal and is responsive to the identifier and the stored data to determine whether some or all of the identifier is stored in the dynamic memory array.

Claims

1. A radio-frequency identification (“

RFID”

) transponder, the RFID transponder comprising;

a memory adapted to store data;

a power supply adapted to power the memory;

wherein, when power ceases to be provided to the memory, the data is maintained therein for a predetermined time period;

wherein the predetermined time period is determined by controlled discharge of the memory; and

wherein the predetermined time period is determined by discharging of the memory through stray leakage paths within the memory.

2. The transponder as claimed in claim 1, wherein the memory is volatile memory.

3. The transponder as claimed in claim 1, wherein the memory is temporary memory.

4. The transponder as claimed in claim 1, wherein the memory is comprised of at least one memory cell.

5. The transponder as claimed in claim 1, wherein the memory is comprised of a memory array.

6. The transponder as claimed in claim 1, wherein the power supply is adapted to also power circuitry associated with the RFID transponder.

7. The transponder as claimed in claim 1, wherein the predetermined time period is a time period longer than a longest periodic power outage.

8. The transponder as claimed in claim 1, wherein the data is first data.

9. The transponder as claimed in claim 1, further comprising a validity memory circuit adapted to be indicative of whether data in the memory is valid.

10. The transponder as claimed in claim 9, wherein, when power ceases to be provided to the RFID transponder, the validity memory circuit discharges before the memory discharges.

11. The transponder as claimed in claim 10, wherein the validity memory circuit discharges via a current sink circuit.

12. The transponder as claimed in claim 9, wherein the validity memory circuit comprises a current source that charges a storage capacitor.

13. The transponder as claimed in claim 9, wherein the validity memory circuit comprises a storage capacitor interoperably connected to a refresh circuit, a current source, a current sink circuit, and an inverter.

14. The transponder as claimed in claim 13, wherein a supply voltage is maintained on the storage capacitor by the refresh circuit, the current source, and the inverter.

15. The transponder as claimed in claim 13, wherein the refresh circuit comprises a first transistor and a second transistor.

16. The transponder as claimed in claim 15, wherein the first transistor is connected between the current sink circuit and the inverter.

17. The transponder as claimed in claim 15, wherein the second transistor is connected between the storage capacitor and the inverter.

18. The transponder as claimed in claim 16, wherein the refresh circuit is operable to prevent the storage capacitor from discharging through the first transistor in an event of power failure.

19. The transponder as claimed in claim 18, wherein the storage capacitor discharges through the current sink circuit.

20. The transponder as claimed in claim 19, wherein the current sink circuit comprises a third transistor and a load.

21. The transponder as claimed in claim 20, wherein the current sink circuit is operable to provide a stable discharge current in the event of power failure.

22. The transponder as claimed in claim 21, wherein a first terminal of the storage capacitor is connected to ground and a second terminal of the storage capacitor is connected to the second transistor.

23. The transponder as claimed in claim 21, wherein a first terminal of the storage capacitor is connected to ground and a second terminal of the storage capacitor is connected to the third transistor.

24. The transponder as claimed in claim 1, wherein the memory stores at least one bit of data.

25. The transponder as claimed in claim 1, wherein the memory comprises a data-storage capacitor interoperably connected to a leakage node.

26. The transponder as claimed in claim 1, wherein the memory is configured to discharge via leakage paths in an event of power failure.

27. The transponder as claimed in claim 1, wherein the memory is configured to discharge only via leakage paths in an event of power failure.

28. The transponder as claimed in claim 1, wherein the data is derived from an interrogator.

29. The transponder as claimed in claim 1, wherein the data is derived from the transponders own memory.

30. The transponder as claimed in claim 1, wherein the data is derived from other circuits on the transponder.

31. The transponder as claimed in claim 1, wherein the memory comprises at least one of:

DRAM;

RAM;

memory adapted to hold data for a period of time longer than a longest periodic power outage; and

an on-board processor.

32. The transponder of claim 31, wherein the on-board processor comprises at least one of a signal processor, a central processor, and associated memory.

33. The transponder as claimed in claim 1, wherein the data comprises at least one of:

a date stamp;

a time stamp number representative of a particular time of transmission;

a number representative of the particular orthogonal orientation;

an identifier signal;

an interrogator reference number;

a unique code for identifying a transponder interrogator;

a pseudo-random number or character string;

a mute bit;

an identification number;

configuration information or settings;

temporary data stored in registers;

a PRBS number;

chopper settings;

a coded string to enable discrimination between other RFID transponders;

power mode control;

identity data adapted to determine the order in which the RFID transponder receives an interrogating signal;

the time of provision of the interrogating signal; and

content and timing of transmission signals between devices.

34. The transponder as claimed in claim 1, wherein the memory is further selectively updated with reference to a time stamp.

35. The transponder as claimed in claim 1, comprising a second power supply to power the memory when power ceases to be provided to the transponder.

36. The transponder as claimed in claim 35, wherein the second power supply comprises a capacitor.

37. The transponder according to claim 1, wherein:

an RFID system provides an interrogating signal having an identifier; and

the RFID transponder comprises a receiver for receiving the interrogating signal.

38. The transponder according to claim 37, comprising a signal processor responsive to:

a) the receiver for extracting the identifier from the signal; and

b) the identifier and the data for determining whether the identifier is stored in the memory.

39. The transponder according to claim 37, wherein the identifier comprises a time stamp and a unique code for identifying a transponder interrogator.

40. The transponder according to claim 1, wherein the power supply provides power by converting an externally-applied electromagnetic excitation field into electrical power.

41. The transponder according to claim 1, further comprising:

a timer for providing a validity flag in response to an interrogating signal;

wherein the flag is valid if the interrogating signal is received within a second time period;

wherein the flag is invalid if the interrogating signal is received after the second time period; and

wherein the data in the volatile memory is maintained in a readable state until at least the expiration of the second time period.

42. The transponder according to claim 41, wherein:

the timer comprises a capacitive cell for storing a charge generated by current from the power supply; and

once power from the power supply ceases to be supplied, the charge in the capacitive cell discharges at a predetermined rate.

43. The transponder according to claim 42, wherein:

the status of the validity flag is based on a voltage generated at a predetermined point in the timer; and

the voltage decays as the capacitive cell discharges.

44. The transponder according to claim 43, wherein the voltage is an output voltage of the capacitive cell as the capacitive cell discharges through a load.

45. The transponder according to claim 42, wherein the capacitive cell is a memory cell.

46. The transponder according to claim 45, wherein the memory cell forms part of the memory.

47. An RFID system comprising:

an RFID transponder as claimed in claim 1, and

a transponder interrogator for providing an interrogation field and reading data from the RFID transponder.

48. The system according to claim 47, wherein:

the transponder interrogator is adapted to sequentially switch an orientation of the interrogation field; and

the time period is selected to exceed the time that the interrogation field is off during switching of the orientation.

49. The RFID system according to claim 47, wherein the interrogator periodically switches orientation of the interrogation field.

50. The RFID system according to claim 49, wherein the interrogation field is switched between orthogonal orientations.

51. The RFID system according to claim 50, wherein a direction of the interrogation field is switched at 10 ms time intervals.

52. The RFID system according to claim 50, wherein a direction of the interrogation field is switched at time intervals greater than 10 ms.

53. The transponder according to claim 1, wherein the memory comprises a plurality of address cells adapted to hold temporary data used by the RFID transponder.

54. The transponder according to claim 1, wherein the predetermined time period is at least a few seconds.

55. The transponder according to claim 1, wherein the RFID transponder is attached to an article being progressed through a device selected from the group consisting of a transponder reader and an RFID interrogator.

56. The transponder according to claim 1, wherein when power from the power supply ceases to be supplied, the memory is isolated from the power supply by a series pass transistor.

57. The transponder according to claim 1, wherein a discharge circuit and a voltage level detector are connected in parallel with the memory.

58. The transponder according to claim 57, wherein the discharge circuit and the voltage level detector are adapted to limit a maximum time the data remains stored in the memory.

59. The transponder according to claim 57, wherein the discharge current is adapted to ensure that the data in the memory is validly maintained during power outages.

60. The transponder according to claim 1, wherein the RFID transponder comprises a transmitter for transmitting a reply signal to a transponder interrogator in response to the interrogating signal.

61. A method of storing data in a radio-frequency identification (“

RFID”

) transponder adapted for use in an RFID system, the method comprising the steps of;

storing data in a memory of the RFID transponder;

providing a first power supply associated with the memory;

validly maintaining the data in the memory for a predetermined time period after power ceases to be provided to the memory by the first power supply; and

wherein the predetermined time period is determined by discharging of the memory through stray leakage paths within the memory.

62. The method as claimed in claim 61, wherein the memory is temporary memory.

63. The method as claimed in claim 61, wherein the memory is volatile memory.

64. The method as claimed in claim 61, wherein the memory is comprised of at least one memory cell.

65. The method as claimed in claim 61, wherein the memory is comprised of a memory array.

66. The method as claimed in claim 61, wherein the data is first data.

67. The method as claimed in claim 61, further comprising the step of enabling the memory to hold data for a period of time longer than a longest periodic power outage.

68. The method as claimed in claim 61, further comprising the step of providing a second power supply to power the memory when the power provided by the first power supply ceases.

69. The method as claimed in claim 61, wherein the data comprises at lease one of:

a date stamp;

a time stamp number representative of the particular time of transmission ;

a number representative of the particular orthogonal orientation;

an identifier signal;

an interrogator reference number;

a unique code for identifying a transponder interrogator;

a pseudo-random number or character string;

a mute bit;

an identification number;

configuration information or settings;

temporary data stored in registers;

a PRBS number;

chopper settings;

a coded string to enable discrimination between other RFID transponders;

power mode control;

identity data adapted to determine the order in which the RFID transponder receives an interrogating signal;

the time of the provision of the interrogating signal; and

content and timing of transmission signals between devices.

70. The method according to claim 61, further comprising:

the RFID system providing an interrogating signal having an identifier; and

wherein the RFID transponder comprises a receiver for receiving the interrogating signal.

71. The method according to claim 70, wherein the RFID transponder comprises a signal processor responsive to:

a) the receiver for extracting the identifier from the signal; and

b) the identifier and the data for determining whether the identifier is stored in the volatile memory array.

72. The method according to claim 61, wherein the memory comprises a memory circuit comprising at least one data-storage capacitor for storing at least part of the data.

73. The method according to claim 72, wherein the at least part of the data is stored on the at least one data storage capacitor via a data-enable terminal.

74. The method according to claim 72, wherein the stored data is available at an output of the memory circuit interoperably coupled to the data-storage capacitor.

75. The method according to claim 72, wherein the stray leakage paths comprise at least one of a leakage path through a transistor interoperably connected to the at least one data-storage capacitor and a leakage path through an output of the memory circuit.

76. The method according to claim 61, wherein the memory comprises a memory circuit comprising at least one data-storage capacitor and wherein the at least one data-storage capacitor receives no power from any other part of the RFID transponder when power ceases to be provided to the memory.

77. The method according to claim 61, wherein the memory comprises a memory circuit comprising at least one data-storage capacitor and wherein the at least one data-storage capacitor does not function as a supplemental power source when power ceases to be provided to the memory.

78. The method according to claim 61, wherein the memory comprises a memory circuit comprising at least one data-storage capacitor and wherein the at least one data-storage capacitor is interoperably connected to a leakage node.

79. The method according to claim 78, wherein the leakage node is present between the at least one data-storage capacitor and a transistor.

80. The method according to claim 78, wherein the leakage node is present between the at least one data-storage capacitor and an inverter.

81. The method according to claim 61, further comprising the steps of:

providing, via a timer, a validity flag in response to an interrogating signal;

wherein the flag is considered valid if the interrogating signal is received within a second time period;

wherein the flag is considered invalid if the interrogating signal is received after the second time period; and

wherein the data in the memory is maintained in a readable state until at least the expiration of the second time period.

82. The method according to claim 81, further comprising the step of:

storing, in a capacitive cell, a charge generated by current from the first power supply.

83. The method according to claim 82, further comprising the step of:

discharging, at a predetermined rate, the charge in the capacitive cell responsive to power from the first power supply ceasing to be supplied.

84. The method according to claim 82, wherein the timer comprises the capacitive cell.

85. The method according to claim 82, wherein the capacitive cell is a memory cell.

86. The method according to claim 85, wherein the memory cell forms part of a memory array.

87. A radio-frequency identification (“

RFID”

) transponder for use in an RFID system, the transponder comprising;

a temporary memory array for storing data;

a first power supply for powering circuitry associated with the RFID transponder, including the temporary memory array;

wherein the RFID transponder is configured such that, when power ceases to be provided to the temporary memory array by the first power supply, the data in the temporary memory array is validly maintained therein for a predetermined time period; and

wherein the temporary memory array comprises DRAM, and the predetermined time period is determined by discharging of the temporary memory array through stray leakage paths within the temporary memory array.

88. The transponder as claimed in claim 87, wherein the temporary memory array is responsive to an interrogating signal from the system for selectively updating the first data.

89. The transponder as claimed in claim 87, wherein the temporary memory array comprises any one of:

DRAM;

EEPROM;

FRAM;

RAM;

memory adapted to hold data for a period of time longer than the longest periodic power outage; and

memory adapted to hold data for a short time after the supply voltage has been removed.

90. The transponder as claimed in claim 87, wherein the data comprises any one or a combination of:

date stamp;

time stamp number representative of the particular time of transmission;

a number representative of the particular orthogonal orientation;

identifier signal;

interrogator reference number;

pseudo random number or character string;

mute bit;

identification number;

configuration information or settings;

temporary data stored in registers;

PRBS number;

chopper settings;

a coded string to enable discrimination between other transponders;

power mode control;

identity data adapted to determine the order in which the transponder receives an interrogating signal; and

the time of the provision of the interrogating signal.

91. The transponder as claimed in claim 87, wherein the temporary memory array is further selectively updated with reference to a time stamp.

92. The transponder as claimed in claim 87, wherein the temporary memory array comprises RAM, and wherein a second power supply is provided to power the temporary memory array when the power provided by the first power supply ceases.

93. The transponder as claimed in claim 92, wherein the second power supply comprises a capacitor.

94. The transponder according to claim 87, wherein the RFID system provides an interrogating signal having an identifier and the transponder comprises a receiver for receiving the signal.

95. The transponder according to claim 94 comprises a signal processor that is responsive to:

a) the receiver for extracting the identifier from the signal; and

b) the identifier and the first data for determining whether the identifier is stored in the temporary memory array.

96. The transponder according to claim 87, wherein the first power supply is configured to provide power by converting an externally applied electromagnetic excitation field into electrical power.

97. The transponder according to claim 87, further comprising a timer means for providing a validity flag in response to an interrogating signal, the flag being “

valid”

if the interrogating signal is received within a second time period and “

invalid”

if the interrogating signal is received after the second time period, the transponder being configured such that the data in the temporary memory array is maintained in a readable state until at least the expiration of the second time period.

98. The transponder according to claim 97, wherein the timer means comprises a capacitive cell for storing a charge generated by current from the first power supply, the timer means being configured such that, once power from the first power supply ceases to be supplied, the charge in the capacitive cell discharges at a predetermined rate.

99. The transponder according to claim 97, wherein the status of the validity flag is based on a voltage generated at a predetermined point in the timer means, the voltage decaying as the capacitive cell discharges.

100. The transponder according to claim 97, wherein the voltage is the output voltage of the capacitive cell as it discharges through a load.

101. The transponder according to claim 100, wherein the capacitive cell is a memory cell.

102. The transponder according to claim 101, wherein the temporary memory array comprises DRAM and the memory cell forms part of the temporary memory array.

103. The RFID system comprising a transponder according to claim 87 and a transponder interrogator for providing an interrogation field and reading data from the transponder.

104. The system according to claim 103, wherein the interrogator is configured to sequentially switch an orientation of the interrogation field, and the second time period is selected to exceed the time that the interrogation field is off during switching of its orientation.