Solid-state imaging device

• US 8,325,256 B2
• Filed: 09/16/2010
• Issued: 12/04/2012
• Est. Priority Date: 10/08/2009
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Egawa, Yoshitaka
• Primary Examiner(s): Fan, Chieh M
• Assistant Examiner(s): CHIU, WESLEY JASON
• Application Number:
  US12/883,819
• Publication Number:
  US 20110085065A1
• Time in Patent Office: 810 Days
• Field of Search: 348/294
• US Class Current: 348/297
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

According to one embodiment, a solid-state imaging device includes, a pixel section, a read pulse amplitude control unit which controls exposure time for which a photo diode carries out the photoelectric conversion and dividing the signal charge accumulated in the photo diode into fractions so that the fractions are read from the photo diode, a plurality of line memories to which the plurality of read signals are saved. And the device further includes an addition unit which synthesizes the plurality of read signals into one signal, the addition unit includes first determination unit which reads the signal saved to the predetermined line memory and comparing a signal level of the read signal with a predetermined level to determine whether or not to add a signal read from a different line memory to the compared signal.

Claims

1. A solid-state imaging device comprising:

a pixel section comprising a plurality of cells arranged on a semiconductor substrate and each comprising a photo diode configured to photoelectrically convert an optical signal into a signal charge, a read unit which reads the signal charge generated by the photo diode, out to a detection section, a output unit which converts the signal charge into a voltage corresponding to a charge amount and then outputting the voltage, and a reset unit which resets the detection section;

a read pulse amplitude control unit which controls exposure time for which the photo diode carries out the photoelectric conversion and dividing the signal charge accumulated in the photo diode into fractions so that the fractions are read from the photo diode;

a plurality of line memories to which the plurality of read signals are saved; and

an addition unit which synthesizes the plurality of read signals into one signal, the addition unit comprising a determination unit which reads the signal saved to a predetermined line memory and comparing a signal level of the read signal with a predetermined level to determine whether or not to add a signal read from a different line memory to the compared signal,

wherein the addition unit further comprises a control switch configured to perform switching such that when a high conversion gain for AD conversion is input, execution of a process of adding together the signals resulting from dividing the signal charges into fractions is avoided.

2. A solid-state imaging device comprising:

a pixel section comprising a plurality of cells arranged on a semiconductor substrate and each comprising a photo diode configured to photoelectrically convert an optical signal into a signal charge, a read unit which reads the signal charge generated by the photo diode, out to a detection section, a output unit which converts the signal charge into a voltage corresponding to a charge amount and then outputting the voltage, and a reset unit which resets the detection section;

a read pulse amplitude control unit which controls exposure time for which the photo diode carries out the photoelectric conversion and dividing the signal charge accumulated in the photo diode into fractions so that the fractions are read from the photo diode;

a plurality of line memories to which the plurality of read signals are saved; and

an addition unit which synthesizes the plurality of read signals into one signal, the addition unit comprising first determination unit which reads the signal saved to a predetermined line memory and comparing a signal level of the read signal with a predetermined level to determine whether or not to add a signal read from a different line memory to the compared signal,

wherein the addition unit further comprises an average calculation circuit configured to calculate an average value for a plurality of horizontal pixels in the plurality of signals read from the photo diode and which are other than the last signal read from the photodiode, and a second determination unit which carries out an addition process on the input signals if the result of the average calculation indicates that the average value is larger than the value of a black level.