Systems and methods for reduced format data processing

• US 8,325,433 B2
• Filed: 01/19/2011
• Issued: 12/04/2012
• Est. Priority Date: 01/19/2011
• Status: Expired due to Fees

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Zhang, Xun, Grundvig, Jeffrey, Annampedu, Viswanath
• Primary Examiner(s): Tzeng, Fred
• Application Number:
  US13/009,067
• Publication Number:
  US 20120182643A1
• Time in Patent Office: 685 Days
• Field of Search: 360/39, 360/40, 360/42, 360/77.02, 360/77.07, 711/115, 711/167, 375/336, 375/360, 318/700, 318/400.27, 702/60
• US Class Current: 360/39
• CPC Class Codes: G11B 20/10027 adjusting the signal strength during recording or reproduction, e.g. variable gain amplifiers optimum power control for optical discs G11B7/125
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403
• CPC Class Codes: G11B 20/14 using self-clocking codes
• CPC Class Codes: G11B 2020/1232 sector, i.e. the minimal addressable physical data unit
• CPC Class Codes: G11B 2020/1267 Address data
• CPC Class Codes: G11B 2220/2516 Hard disks

Abstract

Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples. The zero gain start calculation circuit is operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value.

Claims

1. A data processing circuit, the data processing circuit comprising:

an analog front end circuit operable to receive an analog signal and to provide a series of digital samples corresponding to the analog signal;

a cosine component calculation circuit operable to calculate a cosine component from the series of digital samples;

a sine component calculation circuit operable to calculate a sine component from the series of digital samples; and

a zero phase start calculation circuit operable to provide a phase select output to a location detection circuit.

2. The data processing circuit of claim 1, wherein the analog front end circuit includes an analog to digital conversion circuit that is synchronized to a sampling clock, and wherein the circuit further comprises:

a zero phase start circuit operable to calculate a first zero phase start value based upon a first portion of the series of digital samples, and to calculate a second zero phase start value based upon a second portion of the series of digital samples; and

a frequency error estimation circuit, wherein the frequency error estimation circuit calculates a raw frequency error value based at least in part on the first zero phase start value and the second zero phase start value.

3. The data processing circuit of claim 2, wherein operation of the location detection circuit is done in parallel to operation of the frequency error estimation circuit.

4. The data processing circuit of claim 3, wherein the location detection circuit includes a sector address mark detection circuit.

5. The data processing circuit of claim 2, wherein the sampling clock is generated based at least in part an offset derived from the raw frequency error value.

6. The data processing circuit of claim 2, wherein the cosine component is a first cosine component corresponding to a first portion of the series of digital samples, wherein the sine component is a first sine component corresponding to the first portion of the series of digital samples, wherein the cosine component calculation circuit is further operable to calculate a second cosine component corresponding to a second portion of series of digital samples, wherein the sine component calculation circuit is further operable to calculate a second sine component corresponding to the second portion of series of digital samples, and wherein the first zero phase start value (θ

₁) is calculated in accordance with the following equation;

7. The data processing circuit of claim 6, wherein the frequency error estimation circuit calculates the raw frequency error value in accordance with the following equation:

8. The data processing circuit of claim 1, wherein the cosine calculation circuit is a first discrete Fourier transform circuit, and wherein the sine calculation circuit is a second discrete Fourier transform circuit.

9. The data processing circuit of claim 1, wherein the analog front end circuit includes a variable gain amplifier circuit operable to apply a gain to the analog signal data input corresponding to a gain feedback value and to provide an amplified output, and wherein the data processing circuit further comprises:

a zero gain start calculation circuit operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value.

10. The data processing circuit of claim 9, wherein applying the feedback value to the variable gain amplifier is done while the location detection circuit is operating.

11. The data processing circuit of claim 9, wherein the zero gain start calculation circuit calculates an amplitude as the square root of the sine component squared plus the cosine component squared.

12. The data processing circuit of claim 9, wherein the data processing circuit further comprises:

a selective scaling circuit operable to selectively scale the amplitude based at least in part on a magnitude of the amplitude to yield the gain feedback value.

13. The data processing circuit of claim 1, wherein the data processing circuit is implemented in an integrated circuit.

14. The data processing circuit of claim 1, wherein the data processing circuit is implemented as part of an electronic device selected from a group consisting of:

a hard disk drive and a data transmission device.

15. A method for data processing, the method comprising:

receiving an analog signal, wherein the analog signal includes a repeating signal;

converting the analog signal to a series of digital samples synchronous to a sampling clock;

performing a discrete Fourier transform of a first portion of the series of digital samples to yield a first sine component and a first cosine component;

performing a discrete Fourier transform of a second portion of the series of digital samples to yield a second sine component and a second cosine component;

performing a discrete Fourier transform of a third portion of the series of digital samples to yield a third sine component and a third cosine component;

calculating a frequency error value based at least in part on the first sine component, the second sine component, the first cosine component and the second cosine component;

adjusting the sampling clock based at least in part on the frequency error value;

selecting a best phase based at least in part on the third sine component and the third cosine component; and

performing a pattern detection using the best phase, wherein the pattern detection is performed in parallel with adjusting the sampling clock.

16. The method of claim 15, wherein selecting the best phase is done by calculating a zero phase start value based on the third sine component and the third cosine component.

17. The method of claim 15, wherein calculating the frequency error value includes calculating a first zero start value based on the first sine component and the first cosine component, and calculating a second zero start value based on the second sine component and the second cosine component.

18. The method of claim 17, wherein calculating the first zero start value (θ

₁) is done in accordance with the following equation;

19. The method of claim 18, wherein calculating the frequency error value is calculated in accordance with the following equation:

20. The method of claim 15, wherein the analog signal is a first analog signal, and wherein the method further comprises:

receiving a second analog signal;

performing a variable gain amplification on the second analog signal to yield the first analog signal, wherein a magnitude of the variable gain corresponds to a gain feedback value; and

calculating a zero gain start value based on the third cosine component and the third sine component; and

modifying the gain feedback value based at least in part on the zero gain start value.

21. The method of claim 20, wherein modifying the gain feedback is done during the pattern detection performance.

22. The method of claim 20, wherein the zero gain start value is the square root of the first sine component squared plus the second cosine component squared.

23. A data storage device, the data storage device comprising:

a storage medium operable to maintain information;

a read head disposed in relation to the storage medium and operable to sense the information and to provide an analog signal corresponding to the information, wherein the information includes a repeating signal;

a read circuit comprising;

a variable gain amplifier circuit operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output;

an analog to digital conversion circuit operable to convert the amplified output to a corresponding series of digital samples synchronous to a sampling clock;

a cosine component calculation circuit operable to calculate a cosine component from the series of digital samples;

a sine component calculation circuit operable to calculate a sine component from the series of digital samples;

a zero gain start calculation circuit operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value;

a first zero phase start circuit operable to calculate a first zero phase start value based upon a first portion of the series of digital samples, and to calculate a second zero phase start value based upon a second portion of the series of digital samples;

a frequency error estimation circuit, wherein the frequency error estimation circuit calculates a frequency error value based at least in part on the first zero phase start value and the second zero phase start value;

a clock generation circuit operable to generate the sampling clock base at least in part on the frequency error value;

a second zero phase start circuit operable to calculate a third zero phase start value based upon a third portion of the series of digital samples; and

a location detection circuit operable to detect a defined pattern using a phase selected based upon the third zero phase start value, wherein the location detection circuit operates in parallel to the frequency error estimation circuit.

24. The storage device of claim 23, wherein the cosine calculation circuit is a first discrete Fourier transform circuit, and wherein the sine calculation circuit is a second discrete Fourier transform circuit.

25. The storage device of claim 23, wherein the first zero phase start circuit and the second zero phase start circuit are implemented as the same circuit.