RFID tag with MOS bipolar hybrid rectifier

• US 8,326,256 B1
• Filed: 07/15/2008
• Issued: 12/04/2012
• Est. Priority Date: 07/15/2008
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Kuhn, Jay A.
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US12/173,718
• Time in Patent Office: 1,603 Days
• Field of Search: 455/343.3, 3405721-5727, 327/536
• US Class Current: 455/343.3
• CPC Class Codes: G06K 19/0709 the source being an interrogation field
• CPC Class Codes: H01Q 1/2216 used in interrogator/reader equipment
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The power rectifier is constructed from a pair of hybrid RF rectifier elements that include a MOS transistor. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating regions, while an additional RF control signal is being applied to the gates of the transistors.

Claims

1. A power rectifier for a Radio Frequency Identification tag, comprising:

an antenna input node configured to receive wirelessly an alternating signal; and

a plurality of serially coupled stages, at least one of the stages coupled to the antenna input node, and including a first Hybrid element and a second Hybrid element,

the first Hybrid element including;

a first transistor having an input terminal, an output terminal and a first gate, and

a first device having an input terminal and an output terminal, the second Hybrid element including;

a second transistor having an input terminal, an output terminal and a second gate; and

a second device having an input terminal and an output terminal;

in which the input terminal of the first device is connected to the output terminal of the first transistor to form a first intermediate node that is not connected to any other components, and

the first gate is coupled to the antenna input node,

the first device is not biased by the alternating signal;

the output terminal of the second device is connected to the input terminal of the second transistor to form a second intermediate node that is not connected to any other components,

the second gate is coupled to the antenna input node, and

the second device is one of a PNP transistor, an NPN transistor, a Schottky diode, and a diode-connected native NMOS transistor.

2. The rectifier of claim 1, in which

the first gate is further coupled to the output terminal of the first device.

3. The rectifier of claim 1, in which

the first transistor is a PMOS.

4. The rectifier of claim 1, in which

the first device is a Schottky diode.

5. The rectifier of claim 1, in which

the first device is a native NMOS transistor configured as a diode.

6. The rectifier of claim 1, in which

the input terminal of the first transistor is connected to receive a DC voltage.

7. The rectifier of claim 1, in which

the first device is a NPN transistor.

8. The rectifier of claim 7, in which

the input terminal of the NPN transistor is its collector.

9. The rectifier of claim 7, in which

the first device also includes a base terminal that is coupled to receive a first DC bias voltage.

10. The rectifier of claim 1, in which

the first device is a PNP transistor.

11. The rectifier of claim 1, in which

the second transistor is a NMOS.

12. The rectifier of claim 1, in which

the second gate is coupled to the input terminal of the second device.

13. The rectifier of claim 1, in which

the input terminal of the PNP transistor is its emitter.

14. The rectifier of claim 1, in which

if the second device is a PNP transistor, the second device also includes a base terminal that is coupled to receive a second DC bias voltage.

20. The rectifier of claim 1, wherein the output terminal of the first device is coupled to the input terminal of the second device.

21. The rectifier of claim 2, wherein the first gate is coupled to the output terminal of the first device via a capacitor.

22. The rectifier of claim 12, wherein the second gate is coupled to the input terminal of the second device via a capacitor.

15. A power rectifier for a Radio Frequency Identification tag, comprising:

a first antenna input node configured to receive wirelessly a first alternating signal;

a second antenna input node configured to receive wirelessly a second alternating signal; and

a plurality of serially coupled dual stages, at least one of the dual stages coupled to both the first and second antenna input nodes, and including a first dual Hybrid element that includes;

a first transistor having an input terminal, an output terminal, and a first gate, and

a first device having an input terminal and an output terminal,

in which the output terminal of the first transistor is connected to the input terminal of the first device to form a first intermediate node that is not connected to any other components, and

a second device having an input terminal and an output terminal, and

a second transistor having an input terminal, an output terminal, and a second gate,

in which the input terminal of the second transistor is connected to the output terminal of the second device to form a second intermediate node that is not connected to any other components,

the first gate is coupled to the first antenna input node, while the first device is not biased by an alternating signal,

the second gate is coupled to the second antenna input node, while the second device is not biased by an alternating signal; and

the first and second devices are one of Schottky diodes, diode-connected native NMOS transistors, PNP transistors, and NPN transistors.

16. The rectifier of claim 15, in which

the first gate is further coupled to the output terminal of the first device to receive a DC bias voltage.

17. The rectifier of claim 15, in which

the second gate is coupled to the input terminal of the second device to receive a DC bias voltage.

18. The rectifier of claim 15, in which

the first transistor is a PMOS.

19. The rectifier of claim 15, in which

the second transistor is a NMOS.

23. The rectifier of claim 15, wherein the output terminal of the first device is coupled to the input terminal of the second device.