Synchronized envelope and transient simulation of circuits

• US 8,326,591 B1
• Filed: 11/16/2007
• Issued: 12/04/2012
• Est. Priority Date: 11/16/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Cai, Qian, Feng, Dan, McGaughy, Bruce W., Kong, Jun, Lin, Rendong
• Primary Examiner(s): Kim, Eunhee
• Application Number:
  US11/941,904
• Time in Patent Office: 1,845 Days
• Field of Search: 703/13, 703/14
• US Class Current: 703/13
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.

Claims

1. A method of simulating a circuit comprising:

partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks;

performing a first envelope simulation of the radio-frequency blocks to generate output waveforms of the radio-frequency blocks;

performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks, the second simulation differing from the first envelope simulation; and

synchronizing the first envelope simulation of the radio-frequency blocks and the second simulation of the non-radio frequency blocks together at one or more time steps to generate output waveforms for the circuit.

2. The method of claim 1, wherein

a radio frequency block has a radio frequency signal as its input stimulus.

3. The method of claim 1, wherein

one or more signals present in a radio-frequency block are slowly varying highly cyclic signals.

4. The method of claim 1, further comprising:

interpolating results of the first envelope simulation to determine a solution for input and output signals of the radio-frequency block at a time step to synchronize the first envelope simulation and the second simulation together.

5. The method of claim 4, wherein

the second simulation is a transient simulation,

the envelope simulation skips one or more cycles of its input and output signals, including the solution of the input and output signals at the time step to synchronize the envelope simulation and the transient simulation together, and

the interpolating is a trigonometric interpolation that models a signal over one cycle of a cyclic waveform using a Fourier series and models the modulation of the signal into other cycles of the cyclic waveform of the signal using slowly time-varying Fourier coefficients.

6. The method of claim 1, wherein

at least one non-radio-frequency block is a digital circuit block.

7. The method of claim 1, further comprising:

storing the output waveforms for the circuit in a waveform database.

8. The method of claim 7, further comprising:

prior to the synchronizing, storing the output waveforms of the radio-frequency blocks in the waveform database.

9. A computer program product for simulation of a circuit, comprising:

a non-transitory computer readable storage medium having

computer readable program code embodied therein to partition a circuit into a plurality of circuit blocks, the plurality of circuit blocks including radio frequency circuit blocks and non-radio-frequency blocks;

computer readable program code embodied therein to perform envelope simulation with radio-frequency circuit blocks;

computer readable program code embodied therein to perform transient simulation with non-radio-frequency circuit blocks; and

computer readable program code embodied therein to synchronize the envelope simulation of the radio frequency circuit blocks and the transient simulation of the non-radio frequency circuit blocks together at one or more time steps to form a simulation output for the circuit.

10. The computer program product of claim 9, wherein

the non-transitory computer readable storage medium further having

computer readable program code embodied therein to interpolate results of the envelope simulation to obtain one or more simulation solutions for the radio-frequency circuit blocks at one or more time points skipped over by the envelope simulation.

11. The computer program product of claim 9, wherein

the non-transitory computer readable storage medium further having

computer readable program code embodied therein to adaptively switch between envelope simulation and transient simulation of a radio-frequency circuit block and compare results of the envelope simulation and the transient simulation to determine simulation accuracy.

12. The computer program product of claim 9, wherein

the envelope simulation is a fast envelope simulation;

and

the non-transitory computer readable storage medium further has

computer readable program code embodied therein to check smoothness of input signal changes to the radio-frequency blocks to determine if fast envelope simulation of the radio-frequency circuit blocks is valid, and if the fast envelope simulation of a radio-frequency circuit block is invalid then the radio-frequency block is re-simulated with a different simulation method.

13. The computer program product of claim 12, wherein

the different simulation method to re-simulate the radio-frequency circuit block is transient simulation.

14. The computer program product of claim 9, wherein

at least one non-radio-frequency circuit block is a digital circuit block.

15. The computer program product of claim 9, wherein the simulation output for the circuit are output waveforms and the non-transitory computer readable storage medium further has

computer readable program code embodied therein to store the output waveforms for the circuit in a waveform database.

16. The computer program product of claim 15, wherein the envelope simulation generates output waveforms for the radio-frequency circuit blocks and the non-transitory computer readable storage medium further has

computer readable program code embodied therein to store the output waveforms for the radio-frequency circuit blocks in the waveform database.

17. A simulation system to simulate a design of an integrated circuit including radio-frequency (RF) blocks, the simulation system comprising:

a computing device including

a partitioner to partition the integrated circuit into partitioned circuit blocks including RF blocks and non-RF blocks;

a transient analysis engine in communication with the partitioner, the transient analysis engine to perform transient simulations of the non-RF blocks;

an envelope analysis engine in communication with the partitioner, the envelope analysis engine to perform envelope simulations of the RF blocks; and

a synchronizer in communication with the transient analysis engine and the envelope analysis engine, the synchronizer to periodically synchronize the envelope analysis engine and the transient analysis engine together to synchronize the transient simulations of the non-RF blocks with the envelope simulations of the RF blocks.

18. The simulation system of claim 17, wherein the computing device further includes:

an interpolator in communication with the transient analysis engine and the envelope analysis engine, the interpolator to interpolate results of the envelope simulation by the envelope analysis engine for the transient analysis engine.

19. The simulation system of claim 18, wherein the computing device further includes:

an error controller in communication with the transient analysis engine, the envelope analysis engine, and the synchronizer, the error controller to further synchronize the transient analysis engine and the envelope analysis engine together and control simulation error to provide simulation results.

20. The simulation system of claim 19, wherein

the error controller further to perform local truncation error (LTE) checking on all harmonics used in envelope simulation to be sure transients are settled.

21. The simulation system of claim 18, wherein

the interpolator uses trigonometric interpolation to model a signal over one cycle of a cyclic waveform using a Fourier series and models the modulation of the signal into other cycles of the cyclic waveform of the signal using slowly time-varying Fourier coefficients.

22. The simulation system of claim 19, wherein the computing device further includes a processor and a non-transitory computer readable storage medium to store instructions for execution by the processor.

23. The simulation system of claim 17, wherein

the synchronizer causes the simulation system to perform a method including

performing an initial transient simulation on a plurality of circuit blocks of an integrated circuit over an initial predetermined period of time up to an envelope start time;

performing a local truncation error check of harmonics used in envelope simulation on results of the initial transient simulation;

determining a number of cycles of a cyclic waveform that can be skipped during envelope simulation in response to the local truncation error check;

performing envelope simulation of a first radio-frequency circuit block from the envelope start time to an envelope end time such that a number of sample points and clock cycles are skipped;

trigonometrically interpolating results of the envelope simulation to determine a solution of skipped sample points for the first RF circuit block within the skipped clock cycles; and

providing the solution of the skipped sample points for the first RF circuit block to other circuit blocks and simulating the other circuit blocks at a synchronization time point in response to the solution to synchronize the simulation of the plurality of circuit blocks of the integrated circuit.

24. The simulation system of claim 23, wherein

the synchronizer further causes the simulation system to perform the method including

trigonometrically interpolating the results of the envelope simulation to obtain a solution for input and output signals of the first RF circuit block at the synchronization time;

and

checking smoothness of the input signals at all input ports of the first RF circuit block to validate the envelope simulation.

25. The simulation system of claim 24, wherein

if the smoothness checking indicated that the envelope simulation is invalid at the synchronization time, the synchronizer further causes the simulation system to perform the method including

trigonometrically interpolating the results of the envelope simulation at a time prior to the synchronization time and

performing transient simulation in the first RF circuit block from the prior time to the synchronization time, accepting the solution of the transient simulation at the synchronization time, and continuing the transient simulation in the first RF circuit block until signal transients are settled in the first RF circuit block.

26. The simulation system of claim 24, wherein

the synchronizer causes the simulation system to repeatedly perform the elements of the method for each and every RF circuit block of the integrated circuit.

27. The simulation system of claim 17, wherein

at least one of the non-RF blocks is a digital circuit block.

28. The simulation system of claim 17, further comprising:

a waveform database in communication with the transient analysis engine and the envelope analysis engine, the waveform database to store output waveforms for the integrated circuit.

29. The simulation system of claim 28, wherein

the performance of envelope simulations of the RF blocks by the envelope analysis engine generates output waveforms for the RF blocks;

and

the waveform database further stores the output waveforms for the RF blocks.