Method, system, and apparatus for dynamic reconfiguration of resources

• US 8,327,113 B2
• Filed: 09/23/2008
• Issued: 12/04/2012
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ayyar, Mani, Delano, Eric, Schoinas, Ioannis T., Kumar, Akhilesh, Jayasimha, Jay, Vargas, Jose A.
• Primary Examiner(s): Osman, Ramy M
• Application Number:
  US12/235,968
• Publication Number:
  US 20090024715A1
• Time in Patent Office: 1,533 Days
• Field of Search: 709/221, 709/226, 709/215, 709/201, 712/29, 712/229, 712/15, 714/34, 714/45
• US Class Current: 712/15
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Claims

1. A method for on-line addition of an individual resource comprising:

setting up physical and logical information for the individual resource with inband firmware or a system service processor (SSP), where setting up is performed by a computing device;

defining serial links between a running system (RS) and the individual resource with the inband firmware or the system service processor (SSP);

setting a path to a firmware;

running self-test and initialization on the individual resource with the resource;

indicating to firmware execution on the RS that the individual resource is ready to join at least one partition; and

indicating to an operating system (OS) on the RS that the individual resource is ready to join at least one partition; and

facilitating multiple quiescence operations relating to multiple domains, wherein a quiescence operation is initiated by the inband firmware or the SSP.

2. The method of claim 1, wherein the individual resource is either a processor node, memory only node, or I/O hub node.

3. The method of claim 1, wherein the on-line addition is performed at least in part on the inband firmware being able to quiesce or de-quiesce a domain of interest to update one or more system resources in an atomic operation to a software layer above the inband firmware, wherein the one or more resources include routing tables or address decoders.

4. The method of claim 1, wherein the quiescence operation initiated by the SSP is performed through its non-Common System Interface network or by designating a core that follows in an inband flow.