Reconfigurable FADEC with flash based FPGA control channel and ASIC sensor signal processor for aircraft engine control

• US 8,327,117 B2
• Filed: 08/29/2008
• Issued: 12/04/2012
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: Rolls-Royce Corporation (Rolls-Royce Holdings Plc)
• Original Assignee: Rolls-Royce Corporation (Rolls-Royce Holdings Plc)
• Inventors: Smilg, Lawrence Mitchell, Ernst, James, Zeller, Robert
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US12/201,129
• Publication Number:
  US 20100057957A1
• Time in Patent Office: 1,558 Days
• Field of Search: None
• US Class Current: 712/36
• CPC Class Codes: G05B 19/042 using digital processors G05B19/05 takes precedence

Abstract

A reconfigurable FADEC includes a reconfigurable CPU configured for performing digital computing functions. A reconfigurable MSPD communicates with the CPU and is configured for performing analog I/O functions. A data bus is coupled to the CPU and the MSPD. The data bus is configured for connecting the CPU and the MSPD to an external connector.

Claims

1. A reconfigurable FADEC comprising:

a first programmable device configured as a FADEC control channel for receiving digital sensor information, performing digital computing functions, and producing control outputs responsive to at least the digital sensor information;

a second programmable device receiving analog sensor signals, communicating digital sensor information to the first programmable device, and configured as a mixed-signal processing device for performing analog I/O functions; and

a data bus coupled in communication with the first programmable device, the second programmable device, and an external connector,

wherein the first programmable device consists essentially of a non-volatile flash-based FPGA, the second programmable device is one of an ASIC and an FPGA.

2. A reconfigurable FADEC as defined in claim 1, wherein the second programmable device is configured for sensor signal conditioning, excitation, actuator drives, fault detection, and data bus interfacing.

3. A reconfigurable FADEC as defined in claim 1, wherein the data bus is configured to isolate interactions between the first programmable device and the second programmable device for fault isolation.

4. A reconfigurable FADEC as defined in claim 1, wherein the data bus is configured to have a communications standard compatible with an external PC for performing tests thereon.

5. A reconfigurable FADEC as defined in claim 1, wherein the data bus is configured to a data bus standard selected from one of IEEE 1394, CAN-bus, USB, AFDX, TTP, FireWire, FlexRay, and RS-485.

6. A reconfigurable FADEC as defined in claim 1, wherein the first programmable device and the second programmable device are each configured to be reprogrammable through the data bus.

7. A reconfigurable FADEC as defined in claim 1, wherein the first programmable device is configured to perform data packing for data bus communications and signal filtering.

8. A reconfigurable FADEC as defined in claim 1, wherein the data bus is an external data bus and is configured to allow additional devices to be connected thereto as an upgrading feature.

9. A reconfigurable FADEC as defined in claim 8, wherein the additional devices include sensor I/O, computing, and data storage for engine monitoring.

10. A reconfigurable FADEC as defined in claim 1, further comprising a power supply configured to select between aircraft and PMA power.

11. A reconfigurable FADEC as defined in claim 1, further comprising a power supply configured to condition PMA power to the voltage necessary to power the FADEC.

12. A reconfigurable FADEC as defined in claim 1, further comprising a scaleable power supply configured to adjust DC power level to distribute the necessary power to operate the FADEC so as to allow the ability to scale the power supply as the functions of the FADEC scale.