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Reconfigurable FADEC with flash based FPGA control channel and ASIC sensor signal processor for aircraft engine control

  • US 8,327,117 B2
  • Filed: 08/29/2008
  • Issued: 12/04/2012
  • Est. Priority Date: 08/29/2008
  • Status: Active Grant
First Claim
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1. A reconfigurable FADEC comprising:

  • a first programmable device configured as a FADEC control channel for receiving digital sensor information, performing digital computing functions, and producing control outputs responsive to at least the digital sensor information;

    a second programmable device receiving analog sensor signals, communicating digital sensor information to the first programmable device, and configured as a mixed-signal processing device for performing analog I/O functions; and

    a data bus coupled in communication with the first programmable device, the second programmable device, and an external connector,wherein the first programmable device consists essentially of a non-volatile flash-based FPGA, the second programmable device is one of an ASIC and an FPGA.

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