Apparatus and methods for programmable power-up sequence

• US 8,327,163 B2
• Filed: 11/12/2009
• Issued: 12/04/2012
• Est. Priority Date: 02/27/2009
• Status: Active Grant

• Current Assignee: Global UniChip Corp., Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Global UniChip Corp., Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shi-Hao
• Primary Examiner(s): Rehman, Mohammed
• Application Number:
  US12/617,572
• Publication Number:
  US 20100219866A1
• Time in Patent Office: 1,118 Days
• Field of Search: 713/300
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

Circuits and methods for providing control of a power up sequence for supplying a gated power supply to a circuit portion. A power switch fabric is provided having more than two chains with more than two bits of control. The chains include power switches that are sequentially enabled in response to control signal to supply a virtual power supply to a gated circuit to support power gating. The power switches may include daughter switches and mother switches, where the mother switches are enabled later in time than the daughter switches. The enable signals to allow the virtual power supply to begin powering up may be timed to control the ramp up time, in rush current and peak current during the power up sequence of the virtual power supply. Methods for providing timing for the daughter and mother switches and enables to multiple chains in a power switch fabric are disclosed.

Claims

1. An apparatus for providing a virtual power supply to a circuit portion of an integrated circuit, comprising:

a plurality of power switches coupled in at least two independent chains between a plurality of VDD conductors coupled to a power supply and virtual VDD conductors providing the virtual power supply, having control signals coupled in sequence to an enable signal to sequentially turn on;

the plurality of VDD conductors disposed over the circuit portion and arranged in parallel to one another and extending in a first direction;

a plurality of the virtual VDD conductors disposed over the circuit portion arranged in parallel to one another and extending in a second direction different from the first direction and intersecting at least two of the VDD conductors, each of the plurality of virtual VDD conductors coupled to at least two of the power switches coupled in at least two independent chains; and

an enable control circuit providing enable signals to the chains at predetermined times;

wherein the virtual power supply is provided on the virtual VDD conductors coupled to each of the power switches, and the power switches in the independent chains are configured so that the virtual VDD conductors may receive the virtual power supply even if a break in one of the independent chains occurs, and the portion of the circuit is powered on by enabling the power switches.

2. The apparatus of claim 1, and further comprising:

wherein a power switch is provided at an intersection of each one of the plurality of VDD conductors and a virtual VDD conductor.

3. The apparatus of claim 1, and further comprising:

at least one root location providing the power supply to one or more of the chains.

4. The apparatus of claim 3 wherein there are multiple root locations.

5. The apparatus of claim 1, wherein each of the independent chains comprises a chain of daughter switches and a chain of mother switches, each of the mother switches corresponding to one of the daughter switches.

6. The apparatus of claim 5 wherein each of the mother and the daughter switches comprises a PMOS transistor having its current conduction path coupled between the power supply and the virtual power supply and having a gate signal coupled to an enable signal.

7. The apparatus of claim 5 wherein the daughter switches are enabled to provide a power up sequence applying the power supply to the virtual power supply, and the mother switches are enabled at a later time to provide additional current to the virtual power supply.

8. The apparatus of claim 7, wherein the mother switches have their enable signals coupled to the enable signals of the corresponding daughter switches and to a gating circuit that enables the mother switches only after the virtual power supply reaches a threshold voltage.

9. The apparatus of claim 8 wherein the threshold voltage is approximately equal to the power supply voltage.

10. The apparatus of claim 1 wherein the switches comprise PMOS transistors having their current conduction path coupled between the power supply and the virtual power supply and their gate signal coupled to an enable signal.

11. An integrated circuit having at least one circuit coupled to a gated virtual power supply, comprising:

at least one pad for receiving an external power supply;

a circuit portion that has active and inactive modes which is coupled to the gated virtual power supply;

a control circuit providing a plurality of enable signals to apply the external power to the virtual power supply; and

a power switch fabric, further comprising;

a plurality of VDD conductors coupled to the external power supply and arranged in parallel and extending in a first direction overlying the circuit portion;

a plurality of virtual VDD conductors arranged in parallel and extending in a second direction different from the first and overlying the circuit portion, each of the virtual VDD conductors intersecting the VDD conductors; and

a plurality of power chains coupled to supply virtual VDD conductors with the gated virtual power supply to the circuit portion, each power chain comprising a plurality of power switches coupled between the VDD conductors and the virtual VDD conductors and the power switches coupling each of the virtual VDD conductors to at least two of the power chains responsive to one of the enable signals, wherein the virtual VDD conductors may receive the gated virtual power supply even if one of the power chains is broken.

12. The integrated circuit of claim 11 wherein a power switch is disposed at the intersections of the VDD conductors and the virtual VDD conductors.

13. The integrated circuit of claim 12 wherein a break in a chain of the power switch fabric does not break the virtual power supply.

14. The integrated circuit of claim 11 wherein each of the power switches comprises a PMOS transistor having its current conduction path coupled between the power supply and the virtual power supply, and having a gate signal coupled to an enable signal.

15. The integrated circuit of claim 11 wherein one of more of the power chains further comprises a plurality of daughter switches and a plurality of mother switches, the mother switches being enabled at a time after the daughter switches are enabled.

16. The integrated circuit of claim 15, wherein the mother switches further comprise a MOS transistor biased to conduct in linear mode and wherein the daughter switches further comprise a MOS transistor biased to conduct in saturation mode.

17. A method for providing a virtual power supply to a portion of a circuit, comprising:

providing a plurality of VDD conductors coupled to a power supply and arranged in parallel and extending in a first direction and overlying the portion of the circuit;

providing a plurality of virtual power conductors arranged in parallel and extending in a second direction different from the first direction and overlying the portion of the circuit to supply the virtual power supply;

arranging a plurality of power switches coupled between the VDD conductors and the plurality of virtual power conductors in switch fabric chains independently enabled in response to at least two enable signals;

providing a control circuit for supplying the at least two enable signals; and

the plurality of power switches being arranged so that each one of the plurality of virtual power conductors intersects at least two of the VDD conductors and is coupled to at least two of the switch fabric chains, so that each of the virtual power conductors may receive the power supply even if one of the independently enabled switch fabric chains is broken.

18. The method of claim 17 and further comprising:

for each of the chains, arranging a first plurality of power switches as daughter switches and a second corresponding plurality of switches as mother switches, the mother switches being enabled at a time after the corresponding daughter switch is enabled.

19. The method of claim 18 wherein the enable to a mother switch is further gated by a delay circuit that enables the mother switch only after the virtual power supply reaches a predetermined threshold voltage.